公开(公告)号：US20240258214A1

公开(公告)日：2024-08-01

申请号：US18162144

申请日：2023-01-31

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Kengo AOYA

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L23/49565 ,  H01L21/561 ,  H01L21/565 ,  H01L23/3107 ,  H01L24/48 ,  H01L2224/48175

Abstract: An example electronic device includes a substrate having a die pad and a semiconductor device on the die pad electrically connected to the substrate. The device also includes a mold compound over the semiconductor device to provide a packaged electronic device. The packaged electronic device has respective side edges that extend from a first end to terminate in a second end at a distal surface of the mold compound that is spaced apart from the substrate. At least one side edge of the mold compound has a respective surface that is orthogonal to the distal surface and includes a notch extending inwardly from the respective surface.

公开(公告)号：US20240213178A1

公开(公告)日：2024-06-27

申请号：US18595905

申请日：2024-03-05

Applicant: Texas Instruments Incorporated

Inventor： Tomoko NOGUCHI ,  Mutsumi MASUMOTO ,  Kengo AOYA ,  Masamitsu MATSUURA

IPC: H01L23/552 ,  H01L21/56 ,  H01L21/683 ,  H01L21/78 ,  H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L23/552 ,  H01L21/561 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3114 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/48 ,  H01L2224/48245

Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.

公开(公告)号：US20220068556A1

公开(公告)日：2022-03-03

申请号：US17002283

申请日：2020-08-25

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Yi YAN ,  Kengo AOYA ,  Tomoko NOGUCHI ,  Tatsuhiro SHIMIZU

IPC: H01F27/32 ,  H01F41/14 ,  H01F27/29 ,  H01F1/04

Abstract: In examples, a transformer device comprises a first magnetic member; a second magnetic member; and a substrate layer between the first and second magnetic members. The substrate layer comprises a transformer coil. The transformer device includes a third magnetic member inside the substrate layer. The transformer coil encircles the third magnetic member. The third magnetic member physically separates from the first and second magnetic members.

公开(公告)号：US20220352055A1

公开(公告)日：2022-11-03

申请号：US17246056

申请日：2021-04-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Makoto YOSHINO ,  Kengo AOYA

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/49 ,  H01L21/48 ,  H01L21/56

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.

公开(公告)号：US20240379509A1

公开(公告)日：2024-11-14

申请号：US18781062

申请日：2024-07-23

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Makoto YOSHINO ,  Kengo AOYA

IPC: H01L23/495 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31 ,  H01L23/49

Abstract: In some examples, a semiconductor package includes a semiconductor die having a device side and a non-device side opposing the device side. The device side has a circuit formed therein. The package includes a first conductive member having a first surface coupled to the non-device side of the semiconductor die and a second surface opposing the first surface. The second surface is exposed to a top surface of the semiconductor package. The package includes a second conductive member exposed to an exterior of the semiconductor package and coupled to the device side of the semiconductor die. The package includes a plurality of wirebonded members coupled to the second surface of the first conductive member and exposed to the exterior of the semiconductor package. At least one of the wirebonded members in the plurality of wirebonded members has a gauge of at least 5 mils.

公开(公告)号：US20230095630A1

公开(公告)日：2023-03-30

申请号：US17491394

申请日：2021-09-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Makoto SHIBUYA ,  Masamitsu MATSUURA ,  Kengo AOYA

IPC: H01L23/31 ,  H01L23/528 ,  H01L23/00

Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.

公开(公告)号：US20220208689A1

公开(公告)日：2022-06-30

申请号：US17139417

申请日：2020-12-31

Applicant: Texas Instruments Incorporated

Inventor： Tomoko NOGUCHI ,  Mutsumi MASUMOTO ,  Kengo AOYA ,  Masamitsu MATSUURA

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/00 ,  H01L23/498 ,  H01L21/78 ,  H01L21/56 ,  H01L21/683

Abstract: A semiconductor device includes a semiconductor die having a top side surface comprising a semiconductor material including circuitry therein having bond pads connected to nodes in the circuitry, a bottom side surface, and sidewall surfaces between the top side surface and the bottom side surface. A metal coating layer including a bottom side metal layer is over the bottom side surface that extends continuously to a sidewall metal layer on the sidewall surfaces. The sidewall metal layer defines a sidewall plane that is at an angle from 10° to 60° relative to a normal projected from a bottom plane defined by the bottom side metal layer.

公开(公告)号：US20210125959A1

公开(公告)日：2021-04-29

申请号：US16663089

申请日：2019-10-24

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Masamitsu MATSUURA ,  Kengo AOYA ,  Mutsumi MASUMOTO

IPC: H01L23/00 ,  H01L23/552 ,  H01L21/683 ,  H01L21/78

Abstract: In some examples, a wafer chip scale package (WCSP) comprises a die; multiple electrically conductive terminals coupled to a first surface of the die; and a metal covering abutting five surfaces of the die besides the first surface, each of the five surfaces of the die lying in a different plane.