中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

9 records (took 0.018 seconds)

    SEMICONDUCTOR PACKAGES WITH SIDE-FACING AMBIENT LIGHT SENSORS
    1.
    发明公开
    SEMICONDUCTOR PACKAGES WITH SIDE-FACING AMBIENT LIGHT SENSORS 审中-公开

    公开(公告)号：US20240178329A1

    公开(公告)日：2024-05-30

    申请号：US18072456

    申请日：2022-11-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Masamitsu MATSUURA

    IPC: H01L31/0203 ,  H01L31/02 ,  H01L31/18

    CPC classification number: H01L31/0203 ,  H01L31/02002 ,  H01L31/18

    Abstract: In examples, a semiconductor package comprises a semiconductor die including an ambient light sensor, the ambient light sensor facing a horizontal direction. The package includes first and second conductive terminals wirebonded to the semiconductor die, each of the first and second conductive terminals having first and second segments. The package includes a clear mold compound covering the semiconductor die and portions of the first and second conductive terminals. The first segments of the first and second conductive terminals extend vertically through the clear mold compound to an exterior of the clear mold compound, and wherein the second segments of the first and second conductive terminals are positioned exterior to the clear mold compound, extend horizontally in opposing directions, and are adapted to be coupled to a printed circuit board.

    DUAL DOWN-SET CONDUCTIVE TERMINALS FOR EXTERNALLY MOUNTED PASSIVE COMPONENTS
    5.
    发明公开
    DUAL DOWN-SET CONDUCTIVE TERMINALS FOR EXTERNALLY MOUNTED PASSIVE COMPONENTS 审中-公开

    公开(公告)号：US20240222212A1

    公开(公告)日：2024-07-04

    申请号：US18090273

    申请日：2022-12-28

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Masamitsu MATSUURA

    IPC: H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L25/00

    CPC classification number: H01L23/3114 ,  H01L21/565 ,  H01L24/48 ,  H01L25/50 ,  H01L2224/48247

    Abstract: In some examples, a semiconductor package comprises a first die pad having a first top surface and a first bottom surface opposing the first top surface and a second die pad in horizontal alignment with the first die pad, the second die pad having a second top surface and a second bottom surface opposing the second top surface, a gap separating the first and second die pads. The package comprises a semiconductor die electrically coupled to the first and second bottom surfaces and extending across the gap, the semiconductor die having a device side including circuitry formed therein, the device side facing away from the first and second die pads. The package comprises a first conductive terminal extending from a lateral surface of the first die pad and away from the first die pad, the first conductive terminal having multiple down-sets. The package comprises a second conductive terminal extending from a lateral surface of the second die pad and away from the second die pad, the second conductive terminal having multiple down-sets. The package comprises a third conductive terminal having fewer down-sets than the first and second conductive terminals and extending from below the first die pad and away from the first die pad. The package comprises a bond wire coupling the device side of the semiconductor die to the third conductive terminal. The package comprises a mold compound covering the semiconductor die and the bond wire, the first and second die pads exposed to an exterior of the mold compound through a top surface of the mold compound. The package comprises a passive electrical component external to the mold compound and having a first electrical contact coupled to the first die pad and having a second electrical contact coupled to the second die pad. The first, second, and third conductive terminals include distal ends that are exposed through a common side surface of the mold compound, the distal ends in horizontal alignment with each other.

    LEADED WAFER CHIP SCALE PACKAGES
    7.
    发明申请
    LEADED WAFER CHIP SCALE PACKAGES 有权

    公开(公告)号：US20230095630A1

    公开(公告)日：2023-03-30

    申请号：US17491394

    申请日：2021-09-30

    Applicant: TEXAS INSTRUMENTS INCORPORATED

    Inventor： Makoto SHIBUYA ,  Masamitsu MATSUURA ,  Kengo AOYA

    IPC: H01L23/31 ,  H01L23/528 ,  H01L23/00

    Abstract: In examples, a wafer chip scale package (WCSP) comprises a semiconductor die including a device side having circuitry formed therein. The WCSP includes a redistribution layer (RDL) including an insulation layer abutting the device side and a metal trace coupled to the device side and abutting the insulation layer. The WCSP includes a conductive member coupled to the metal trace, the conductive member in a first vertical plane that is positioned no farther than a quarter of a horizontal width of the semiconductor die from a vertical axis extending through a center of the semiconductor die. The WCSP includes a lead coupled to the conductive member and extending horizontally past a second vertical plane defined by a perimeter of the semiconductor die.

Patent Agency Ranking