-
公开(公告)号:US20250047246A1
公开(公告)日:2025-02-06
申请号:US18362017
申请日:2023-07-31
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor: Rajendrakumar JOISH
Abstract: An amplifier circuit includes first and second transistors, and a first current source. The first current source is coupled to first terminals of the first and second transistors. The first current source includes a second current source, and third, fourth, fifth, and sixth transistors. The third transistor has a first terminal coupled to a first terminal of the fourth transistor, and a control terminal coupled to a control terminal of the first transistor. The fourth transistor has a control terminal coupled to a control terminal of the second transistor. The fifth transistor has a first terminal coupled to a first terminal of the sixth transistor, a second terminal coupled to the second current source and to the second terminals of the third, fourth, and sixth transistors, and a control terminal coupled to a control terminal of the sixth transistor.
-
公开(公告)号:US20160079925A1
公开(公告)日:2016-03-17
申请号:US14852004
申请日:2015-09-11
Applicant: Texas Instruments Incorporated
Inventor: Rajendrakumar JOISH
CPC classification number: H03F3/19 , H03F1/0205 , H03F1/0277 , H03F1/22 , H03F1/223 , H03F1/3211 , H03F3/191 , H03F3/45 , H03F3/45098 , H03F3/45103 , H03F2200/111 , H03F2200/294 , H03F2200/451 , H03F2200/546 , H03F2203/45296 , H03F2203/45396
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.
Abstract translation: 本公开提供一种放大器。 放大器包括接收第一输入并产生第一负载电流的第一晶体管。 第一输出节点通过第一负载电阻耦合到电源。 第一个负载电阻接收第一个负载电流。 第一电容器网络耦合到第一输出节点并且从第一输出节点抽取第一电容电流。 第一电流缓冲器耦合在第一输出节点和第一晶体管之间。 通过第一电流缓冲器的电流是第一负载电流和第一电容电流的总和。
-
公开(公告)号:US20170359035A1
公开(公告)日:2017-12-14
申请号:US15620171
申请日:2017-06-12
Applicant: Texas Instruments Incorporated
Inventor: Shagun DUSAD , Rajendrakumar JOISH
CPC classification number: H04B1/40 , G11C27/026 , H03F3/193 , H03F3/45188 , H03F3/505 , H03F2200/451 , H03F2203/45514 , H03F2203/45551 , H03F2203/5024 , H03M1/1245
Abstract: The disclosure provides a circuit. The circuit includes a gain stage block. The gain stage block is coupled to an input voltage through a first switch. A first capacitor is coupled between the first switch and a ground terminal. A second capacitor is coupled between the first switch and a second switch. A third switch is coupled between the second capacitor and a fixed terminal of the gain stage block.
-
公开(公告)号:US20160079945A1
公开(公告)日:2016-03-17
申请号:US14843045
申请日:2015-09-02
Applicant: Texas Instruments Incorporated
Inventor: Rajendrakumar JOISH
CPC classification number: H03G1/0082 , H03F1/26 , H03F3/45085 , H03F3/45098 , H03F3/72 , H03F2200/294 , H03F2203/45026 , H03F2203/45202 , H03F2203/45466 , H03F2203/45494 , H03F2203/45496 , H03F2203/45504 , H03F2203/7233 , H03G1/0035 , H03G1/0088 , H03G3/001 , H03G3/3052 , H04B1/1036 , H04B1/18
Abstract: The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input. A second transistor receives a second input. A plurality of impedance networks is coupled between the first transistor and the second transistor. At least one impedance network of the plurality of impedance networks includes a first impedance path and a second impedance path. The first impedance path is activated during single ended operation, and the second impedance path is activated during differential operation.
Abstract translation: 本公开提供一种放大器。 放大器包括接收第一输入的第一晶体管。 第二晶体管接收第二输入。 多个阻抗网络耦合在第一晶体管和第二晶体管之间。 多个阻抗网络中的至少一个阻抗网络包括第一阻抗路径和第二阻抗路径。 第一阻抗路径在单端操作期间被激活,并且第二阻抗路径在差分操作期间被激活。
-
-
-