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公开(公告)号：US11489517B2
公开(公告)日：2022-11-01
申请号：US17558794
申请日：2021-12-22
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Ram Narayan Krishna Nama Mony , Pooja Sundar
Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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公开(公告)号：US11239833B2
公开(公告)日：2022-02-01
申请号：US17071302
申请日：2020-10-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sriram Murali , Jaiganesh Balakrishnan , Ram Narayan Krishna Nama Mony , Pooja Sundar
Abstract: A circuit includes a noise generator and a delay element. The output of the noise generator couples to the input of the delay element. The output of the delay element is coupled to a first input of a logic circuit, and the output of the noise generator is coupled to a second input of the logic circuit. The output of the logic circuit is coupled to a first control input of a waveform storage circuit. The waveform storage circuit is configured to produce a first digital waveform on its output responsive to a first logic state on the output of the logic circuit and to produce a second digital waveform on its output responsive to a second logic state on the output of the logic circuit. A sequencer has a sequencer output coupled to the second control input of the waveform storage circuit.
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Patent Agency Ranking
公开(公告)号：US11063618B2
公开(公告)日：2021-07-13
申请号：US16943432
申请日：2020-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sashidharan Venkatraman , Jawaharlal Tangudu , Sarma Sundareswara Gunturi , Ram Narayan Krishna Nama Mony
Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.
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4.发明授权公开(公告)号：US10812294B2
公开(公告)日：2020-10-20
申请号：US16684842
申请日：2019-11-15
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Jawaharlal Tangudu , Sashidharan Venkatraman , Sarma Sundareswara Gunturi , Chandrasekhar Sriram , Sthanunathan Ramakrishnan , Ram Narayan Krishna Nama Mony
Abstract: A channel estimation method and system for IQ imbalance and local oscillator leakage correction, wherein an example of a channel estimation system comprising a calibrating signal generator configured to generate at least one pair of calibrating signals, a feedback IQ mismatch estimator configured to measure feedback IQ mismatch estimates based on the pair of calibrating signals, and a calibrating signal based channel estimator configured to generate a channel estimate based on the pair of calibrating signals and the feedback IQ mismatch estimates.
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公开(公告)号：US20240364374A1
公开(公告)日：2024-10-31
申请号：US18645599
申请日：2024-04-25
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sarma Sundareswara Gunturi , Nishant Kumar , Chandrasekhar Sriram , Jawaharlal Tangudu , Ram Narayan Krishna Nama Mony , Varun Padavu Devaraj . , Sashidharan Venkatraman , Pankaj Gaur
IPC: H04B1/04
CPC classification number: H04B1/0475 , H04B2001/0408
Abstract: A circuit includes a capture subsystem and digital pre-distortion (DPD) circuitry. The capture subsystem is configured to capture a set of signal samples responsive to a capture enable signal. The DPD circuitry is configured to generate a signal statistics signal based on an input signal, generate a set of DPD coefficients based on the set of signal samples, and apply DPD correction to the input signal to produce an output signal based on the signal statistics signal and the set of DPD coefficients. The set of signal samples includes samples of the signal statistics signal.
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公开(公告)号：US11533068B1
公开(公告)日：2022-12-20
申请号：US17462145
申请日：2021-08-31
Applicant: Texas Instruments Incorporated
Inventor： Rahul Sharma , Karthikeyan Gunasekaran , Sarma Sundareswara Gunturi , Ram Narayan Krishna Nama Mony , Jaiganesh Balakrishnan , Sandeep Kesrimal Oswal , Visvesvaraya Pentakota
Abstract: A radio frequency transmitter includes an upconverter that outputs in-phase (I) and quadrature (Q) signals, a digital timing offset circuit, first and second digital-to-analog converters (DACs), an analog timing offset removal circuit, first and second pulse shapers, and an adder. The digital timing offset circuit introduces a time offset between the I and Q signals. The first and second DACs output analog I and Q signals, respectively, and have first and second clock signals, respectively. The first and second clock signals have the same frequency and are offset relative to each other by the time offset. The analog timing offset removal circuit removes the time offset between the analog I and Q signals. The first and second pulse shapers receive the analog I and Q signals, respectively, and output pulse-shaped I and Q signals. The adder receives the pulse-shaped I and Q signals and outputs an intermediate frequency signal.
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公开(公告)号：US20210083697A1
公开(公告)日：2021-03-18
申请号：US16943432
申请日：2020-07-30
Applicant: TEXAS INSTRUMENTS INCORPORATED
Inventor： Sashidharan Venkatraman , Jawaharlal Tangudu , Sarma Sundareswara Gunturi , Ram Narayan Krishna Nama Mony
Abstract: An IQ mismatch estimation circuit includes a raw channel estimation circuit, a reference channel estimation circuit, a digital predistortion (DPD) bin identification circuit, a channel estimate pruning circuit, and an IQ correction coefficient generation circuit. The raw channel estimation circuit generates raw channel estimates for a plurality of frequency bins of a baseband signal. The reference channel estimation circuit identifies a reference channel estimate based on the raw channel estimates. The DPD bin identification circuit identifies, based on the reference channel estimate, the frequency bins for which the raw channel estimates are based on a DPD expansion signal. The channel estimate pruning circuit generates pruned raw channel estimates by discarding the raw channel estimates of the frequency bins identified by the DPD bin identification circuit. The IQ correction coefficient generation circuit generates IQ mismatch correction coefficients based on the pruned raw channel estimates.
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