公开(公告)号：US20250105185A1

公开(公告)日：2025-03-27

申请号：US18402944

申请日：2024-01-03

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Gao-Long Wu ,  Shin-Jiun Fu

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/522 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

Abstract: A method includes forming a function circuit on a semiconductor substrate of a device die, wherein the function circuit is in a functional circuit zone of the device die, forming a passive device over the semiconductor substrate, wherein the passive device is in a passive device zone of the device die, forming a first plurality of bond pads in the functional circuit zone and at a surface of the device die, wherein the first plurality of bond pads have a first pattern density; and forming a second plurality of bond pads in the passive device zone and at the surface of the device die. The second plurality of bond pads have a second pattern density lower than the first pattern density.

公开(公告)号：US20250105172A1

公开(公告)日：2025-03-27

申请号：US18543799

申请日：2023-12-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Kuo-Chiang Ting ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Ming-Zhi Yang ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/538

Abstract: An embodiment includes a method including forming a first interconnect structure over a first substrate, the first interconnect structure including dielectric layers and metallization patterns therein. The method also includes forming a redistribution via and a redistribution pad over the first interconnect structure, the redistribution via and the redistribution pad being electrically coupled to at least one of the metallization patterns of the first interconnect structure, the redistribution via and the redistribution pad having a same material composition. The method also includes forming a warpage control dielectric layer over the redistribution pad. The method also includes forming a bond via and a bond pad over the redistribution pad, the bond pad being in the warpage control dielectric layer, the bond via being electrically coupled to the redistribution pad.

公开(公告)号：US20240055371A1

公开(公告)日：2024-02-15

申请号：US18151556

申请日：2023-01-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Der-Chyang Yeh ,  Kuo-Chiang Ting ,  Yu-Hsiung Wang ,  Chao-Wen Shih ,  Sung-Feng Yeh ,  Ta Hao Sung ,  Cheng-Wei Huang ,  Yen-Ping Wang ,  Chang-Wen Huang ,  Sheng-Ta Lin ,  Li-Cheng Hu ,  Gao-Long Wu

IPC: H01L23/00 ,  H01L23/58 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/562 ,  H01L23/585 ,  H01L23/481 ,  H01L23/3178 ,  H01L21/565

Abstract: Embodiments include a crack stopper structure surrounding an embedded integrated circuit die, and the formation thereof. The crack stopper structure may include multiple layers separated by a fill layer. The layers of the crack stopper may include multiple sublayers, some of the sublayers providing adhesion, hardness buffering, and material gradients for transitioning from one layer of the crack stopper structure to another layer of the crack stopper structure.