公开(公告)号：US20240405096A1

公开(公告)日：2024-12-05

申请号：US18328207

申请日：2023-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yun Chen Teng ,  Szu-Ying Chen ,  Yung-Chung Chen ,  Sen-Hong Syue ,  Chi On Chui

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/06 ,  H01L29/423 ,  H01L29/775

Abstract: A method includes etching a first trench in a semiconductor substrate to form a first fin and a second fin, and forming a shallow trench isolation (STI) region in the first trench, where forming the STI region includes depositing a first dielectric layer over top surfaces of the first fin and the second fin, and on sidewalls and a bottom surface of the first trench, the first dielectric layer including carbon, depositing a second dielectric layer over the first dielectric layer, and in the first trench, where the second dielectric layer fills the first trench, and performing an anneal process, where the anneal process releases carbon from the first dielectric layer into the second dielectric layer.