公开(公告)号：US20220068355A1

公开(公告)日：2022-03-03

申请号：US17006882

申请日：2020-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hua-Hsin Yu ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099 ,  G11C7/10

Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.

公开(公告)号：US09484350B2

公开(公告)日：2016-11-01

申请号：US14039481

申请日：2013-09-27

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Tsung-Hsien Huang ,  Hong-Chen Cheng ,  Cheng-Hung Lee ,  Hung-Jen Liao

IPC: H01L29/76 ,  H01L27/112 ,  G11C7/18 ,  H01L23/522 ,  H01L27/06

CPC classification number: H01L27/1128 ,  G11C7/18 ,  H01L21/76816 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/5283 ,  H01L27/0688 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three dimensional semiconductor device includes a first memory device, a second memory device and a via. The via connects the first memory device to the second memory device.

Abstract translation: 三维半导体器件包括第一存储器件，第二存储器件和通孔。 通孔将第一存储器件连接到第二存储器件。

公开(公告)号：US09449656B2

公开(公告)日：2016-09-20

申请号：US13902439

申请日：2013-05-24

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： I-Han Huang ,  Ming-Yi Lee ,  Chia-En Huang ,  Fu-An Wu ,  Jung-Ping Yang ,  Cheng-Hung Lee

IPC: G11C7/22 ,  G11C7/02 ,  G11C5/14 ,  G11C11/419

CPC classification number: G11C7/02 ,  G11C5/147 ,  G11C11/419

Abstract: A memory includes a plurality of bit cells. Each bit cell includes a bit line and a storage cell coupled to the bit line. A header PMOS transistor is coupled to the storage cell in each bit cell. The header PMOS transistor is at least partially turned off during a write operation by a header control signal.

Abstract translation: 存储器包括多个位单元。 每个位单元包括位线和耦合到位线的存储单元。 标头PMOS晶体管耦合到每个位单元中的存储单元。 标头PMOS晶体管在写入操作期间由头部控制信号至少部分地截止。

公开(公告)号：US11551747B2

公开(公告)日：2023-01-10

申请号：US17213182

申请日：2021-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hung Lee

IPC: G11C11/419 ,  G06F7/544

Abstract: A computation apparatus includes a plurality of memory cells and a plurality of sense amplifiers, in which each of the memory cells includes a memory circuit and a calculation circuit. The memory circuits of the memory cells are configured to receive input values from a plurality of word lines, generate a computation result based on the input values and output the computation result to a bit line. The calculation circuits of the memory cells are configured to receive calculation input values from a plurality of calculation word lines, generate calculation output values based on the calculation input values, and output the calculation output values to a plurality of calculation bit lines. The sense amplifiers are configured to sense the calculation output values from the calculation bit lines to generate sensed values, wherein a value of the computation result is determined based on the sensed values and the calculation output values.

公开(公告)号：US20220310157A1

公开(公告)日：2022-09-29

申请号：US17213182

申请日：2021-03-25

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Cheng-Hung Lee

IPC: G11C11/419 ,  G06F7/544

Abstract: A computation apparatus includes a plurality of memory cells and a plurality of sense amplifiers, in which each of the memory cells includes a memory circuit and a calculation circuit. The memory circuits of the memory cells are configured to receive input values from a plurality of word lines, generate a computation result based on the input values and output the computation result to a bit line. The calculation circuits of the memory cells are configured to receive calculation input values from a plurality of calculation word lines, generate calculation output values based on the calculation input values, and output the calculation output values to a plurality of calculation bit lines. The sense amplifiers are configured to sense the calculation output values from the calculation bit lines to generate sensed values, wherein a value of the computation result is determined based on the sensed values and the calculation output values.

公开(公告)号：US20130235687A1

公开(公告)日：2013-09-12

申请号：US13886120

申请日：2013-05-02

Applicant: Taiwan Semiconductor Manufacturing Company Ltd.

Inventor： Ching-Wei Wu ,  Kuang Ting Chen ,  Cheng-Hung Lee

IPC: G11C7/08

CPC classification number: G11C7/08 ,  G11C7/065

Abstract: A circuit includes a first inverter including a first PMOS transistor and a first NMOS transistor, and a second inverter including a second PMOS transistor and a second NMOS transistor. A first node is connected to gates of the first PMOS transistor and the first NMOS transistor and drains of the second PMOS transistor and the second NMOS transistor. A second node is connected to gates of the second PMOS transistor and the second NMOS transistor and drains of the first PMOS transistor and the first NMOS transistor. The circuit further includes a first capacitor having a first capacitance connected to the first node; and a second capacitor having a second capacitance connected to the second node. The second capacitance is greater than the first capacitance.

Abstract translation: 电路包括：第一反相器，包括第一PMOS晶体管和第一NMOS晶体管;以及第二反相器，包括第二PMOS晶体管和第二NMOS晶体管。 第一节点连接到第一PMOS晶体管和第一NMOS晶体管的栅极以及第二PMOS晶体管和第二NMOS晶体管的漏极。 第二节点连接到第二PMOS晶体管和第二NMOS晶体管的栅极以及第一PMOS晶体管和第一NMOS晶体管的漏极。 电路还包括具有连接到第一节点的第一电容的第一电容器; 以及具有连接到第二节点的第二电容的第二电容器。 第二电容大于第一电容。

公开(公告)号：US11854970B2

公开(公告)日：2023-12-26

申请号：US17816108

申请日：2022-07-29

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Chen ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Kao-Cheng Lin ,  Wei-Min Chan

IPC: H01L23/528 ,  H01L27/092 ,  G06F30/392 ,  H01L21/8238 ,  H10B10/00

CPC classification number: H01L23/528 ,  G06F30/392 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L21/823878 ,  H01L27/092 ,  H10B10/12

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

公开(公告)号：US20230378063A1

公开(公告)日：2023-11-23

申请号：US18362670

申请日：2023-07-31

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Chen ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Kao-Cheng Lin ,  Wei-Min Chan

IPC: H01L23/528 ,  H01L27/092 ,  H01L21/8238 ,  G06F30/392 ,  H10B10/00

CPC classification number: H01L23/528 ,  H01L27/092 ,  H01L21/823814 ,  G06F30/392 ,  H10B10/12 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/823871

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

公开(公告)号：US11450605B2

公开(公告)日：2022-09-20

申请号：US17173750

申请日：2021-02-11

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Chien-Yuan Chen ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh ,  Kao-Cheng Lin ,  Wei-Min Chan

IPC: H01L23/528 ,  H01L27/11 ,  H01L27/092 ,  G06F30/392 ,  H01L21/8238

Abstract: Circuit devices, such as integrated circuit devices, are constructed with combination circuits that include two or more cascading transistors, and one or more metal layers disposed over the cascading transistors. The cascading transistors include multiple internal nodes (e.g., common source/drain regions). The multiple internal nodes are not connected to a common metal stripe (the same metal stripe) in the one or more metal layers. The absence of the connections between the internal nodes and a common metal stripe reduce or eliminate the load on the internal nodes. The transistors in the cascading transistors are independent of each other.

公开(公告)号：US11264081B1

公开(公告)日：2022-03-01

申请号：US17006882

申请日：2020-08-30

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

Inventor： Hua-Hsin Yu ,  Cheng-Hung Lee ,  Hung-Jen Liao ,  Hau-Tai Shieh

IPC: G11C11/4091 ,  G11C11/4074 ,  G11C11/4076 ,  G11C11/4099 ,  G11C7/10

Abstract: The disclosure is directed to a memory circuit, an electronic device, and a method of operating the memory circuit. According to an exemplary embodiment, the disclosure is directed to a memory circuit which includes not limited to a voltage equalizing circuit configured to equalize and pre-charge a first data line and a second data line to a reference voltage, a sense amplifier circuit configured to sense a binary data based on a relative voltage between the first data line and the second data line, a read-out latch circuit configured to receive the binary data which is to be transmitted to an external controller, and a write circuit configured to receive a first signal of the first data line and a second signal of the second data line so as to write the first signal to a first bit line and the second signal to a second bit line.