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公开(公告)号：US20230344467A1
公开(公告)日：2023-10-26
申请号：US18347201
申请日：2023-07-05
CPC分类号： H04B5/005 , H04B5/0093 , H05K3/4673 , H05K1/162 , H05K1/165
摘要： A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.
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公开(公告)号：US20210258045A1
公开(公告)日：2021-08-19
申请号：US17167753
申请日：2021-02-04
摘要： A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.
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公开(公告)号：US11716117B2
公开(公告)日：2023-08-01
申请号：US17167753
申请日：2021-02-04
IPC分类号： H04B3/00 , H04B5/00 , H01L21/20 , H01L21/50 , H01L21/56 , H01L21/60 , H01L23/31 , H01L23/34 , H01L23/48 , H01L23/60 , H01L23/522 , H01L23/528 , H01L25/00 , H01L25/065 , H01L49/02 , H05K3/46 , H05K1/16
CPC分类号： H04B5/005 , H04B5/0093 , H05K1/162 , H05K1/165 , H05K3/4673
摘要： A circuit support structure includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the circuit support structure and includes a first contact pad electrically coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the circuit support structure and includes a second contact pad electrically coupled to the second circuit element.
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4.发明申请公开(公告)号：US20230138281A1
公开(公告)日：2023-05-04
申请号：US17515391
申请日：2021-10-29
发明人： Raul Blecic , Nicola Bertoni
摘要： A laminate transformer includes a multilayer substrate having at least first, second, third, and fourth metal layers. The second metal layer and the third metal layer are separated by a voltage barrier having a thickness. A first multiloop coil has at least a first loop on the first metal layer and at least a second loop on the second metal layer. A second multiloop coil has at least a third loop on the third metal layer and at least a fourth loop on the fourth metal layer. A partial EMI shield for the first multiloop coil is on the second metal layer. A partial EMI shield for the second multiloop coil is on the third metal layer.
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公开(公告)号：US12051657B2
公开(公告)日：2024-07-30
申请号：US17474103
申请日：2021-09-14
IPC分类号： H01L23/64 , H01F27/36 , H01L21/48 , H01L23/498 , H01L23/552 , H01L49/02 , H01F19/00
CPC分类号： H01L23/645 , H01F27/363 , H01L21/4857 , H01L23/49822 , H01L23/552 , H01L28/10 , H01F19/00
摘要： An electronic device includes a multilevel lamination structure having a core layer, dielectric layers and conductive features formed in metal layers on or between respective ones or pairs of the dielectric layers. The core layer and the dielectric layers extend in respective planes of orthogonal first and second directions and are stacked along an orthogonal third direction. The conductive features include a first patterned conductive feature having multiple conductive turns in each of a first pair of the metal layers to form a first winding having a first turn and a final turn adjacent to one another in the same metal layer of the first pair, and a second patterned conductive feature having multiple conductive turns in a second pair of the metal layers to form a second winding having a first turn and a final turn.
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6.发明公开公开(公告)号：US20240120964A1
公开(公告)日：2024-04-11
申请号：US18542381
申请日：2023-12-15
发明人： Giacomo Calabrese , Nicola Bertoni , Misha Ivanov
CPC分类号： H04B5/75 , H04B5/266 , H05K1/162 , H05K1/165 , H05K3/4673
摘要： A package substrate includes a first metal layer, a second metal layer, isolation material containing the first and second metal layers, an isolation circuit, a first plurality of contact pads, and a second plurality of contact pads. The isolation circuit includes a first circuit element in the first metal layer and a second circuit element in the second metal layer and electrically isolated from the first circuit element by the isolation material. The first plurality of contact pads is adapted to be coupled to a first integrated circuit on the package substrate and includes a first contact pad coupled to the first circuit element. The second plurality of contact pads is adapted to be coupled to a second integrated circuit on the package substrate and includes a second contact pad coupled to the second circuit element.
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公开(公告)号：US20220415829A1
公开(公告)日：2022-12-29
申请号：US17474103
申请日：2021-09-14
发明人： Raul Blecic , Nicola Bertoni , Zhemin Zhang
IPC分类号： H01L23/64 , H01L23/498 , H01L23/552 , H01L21/48 , H01L49/02 , H01F27/36
摘要： An electronic device includes a multilevel lamination structure having a core layer, dielectric layers and conductive features formed in metal layers on or between respective ones or pairs of the dielectric layers. The core layer and the dielectric layers extend in respective planes of orthogonal first and second directions and are stacked along an orthogonal third direction. The conductive features include a first patterned conductive feature having multiple conductive turns in each of a first pair of the metal layers to form a first winding having a first turn and a final turn adjacent to one another in the same metal layer of the first pair, and a second patterned conductive feature having multiple conductive turns in a second pair of the metal layers to form a second winding having a first turn and a final turn.
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