公开(公告)号：US20250068516A1

公开(公告)日：2025-02-27

申请号：US18942874

申请日：2024-11-11

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Siva Srinivas KOTHAMASU

IPC: G06F11/10 ,  G06F13/16 ,  G11C5/04 ,  G11C29/04 ,  G11C29/52

Abstract: In described examples, a memory module includes a memory array with a primary access port coupled to the memory array. Error correction logic is coupled to the memory array. A statistics register is coupled to the error correction logic. A secondary access port is coupled to the statistics register to allow access to the statistics register by an external device without using the primary interface.

公开(公告)号：US20160035412A1

公开(公告)日：2016-02-04

申请号：US14813949

申请日：2015-07-30

Applicant: Texas Instruments Incorporated

Inventor： Prajkta VYAVAHARE ,  Rajat CHAUHAN ,  Siva Srinivas KOTHAMASU

IPC: G11C11/4093 ,  H03K17/687 ,  G06F13/10 ,  G11C11/4074

CPC classification number: G11C11/4093 ,  G06F1/3296 ,  G06F13/102 ,  G11C7/1057 ,  G11C11/4074 ,  G11C11/4094 ,  H03K17/687 ,  Y02D10/14

Abstract: The disclosure provides an input/output (IO) circuit powered by an input/output (IO) supply voltage. The IO circuit includes a cutoff circuit that receives a first invert signal, the IO supply voltage, a bias voltage and a pad voltage. An output stage is coupled to the cutoff circuit. The output stage receives a first signal, a second signal and the bias voltage. A pad is coupled to the output stage, and a voltage generated at the pad is the pad voltage. The cutoff circuit and the output stage maintain the pad voltage at logic high when the IO supply voltage transition below a defined threshold.

Abstract translation: 本公开提供了由输入/输出（IO）电源电压供电的输入/输出（IO）电路。 IO电路包括接收第一反相信号，IO电源电压，偏置电压和焊盘电压的截止电路。 输出级与断路电路相连。 输出级接收第一信号，第二信号和偏置电压。 焊盘耦合到输出级，并且在焊盘处产生的电压是焊盘电压。 当IO电源电压转换低于定义的阈值时，截止电路和输出级将焊盘电压保持在逻辑高电平。