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    Three Dimensional Three Semiconductor High-Voltage Capacitors
    2.
    发明申请
    Three Dimensional Three Semiconductor High-Voltage Capacitors 有权
    三维三芯半导体高压电容器

    公开(公告)号：US20150076577A1

    公开(公告)日：2015-03-19

    申请号：US14489403

    申请日：2014-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Xiangzheng Bo ,  Douglas T. Grider

    IPC: H01L49/02 ,  H01L27/115

    CPC classification number: H01L21/28273 ,  H01L27/0629 ,  H01L27/11531 ,  H01L28/60 ,  H01L29/94

    Abstract: An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.

    Abstract translation: 集成电路电容器。 电容器包括基板，第一导体和第一导体与基板之间的第一绝缘区域。 电容器还包括第二导体，在第一导体和第二导体之间的第二绝缘区，第三导体和第一导体与第三导体之间的第三绝缘区。 电容器还包括在第一导体和第四导体之间的第四导体和第四绝缘区域。

    Three dimensional three semiconductor high-voltage capacitors
    4.
    发明授权
    Three dimensional three semiconductor high-voltage capacitors 有权
    三维三极管高压电容器

    公开(公告)号：US09318337B2

    公开(公告)日：2016-04-19

    申请号：US14489403

    申请日：2014-09-17

    Applicant: Texas Instruments Incorporated

    Inventor： Xiangzheng Bo ,  Douglas T. Grider

    IPC: H01L27/108 ,  H01L21/28 ,  H01L27/06 ,  H01L29/94 ,  H01L27/115 ,  H01L49/02

    CPC classification number: H01L21/28273 ,  H01L27/0629 ,  H01L27/11531 ,  H01L28/60 ,  H01L29/94

    Abstract: An integrated circuit capacitor. The capacitor includes a substrate, a first conductor, and a first insulating region between the first conductor and the substrate. The capacitor also includes a second conductor, a second insulating region between the first conductor and the second conductor, a third conductor, and a third insulating region between the first conductor and the third conductor. The capacitor also includes a fourth conductor and a fourth insulating region between the first conductor and the fourth conductor.

    Abstract translation: 集成电路电容器。 电容器包括基板，第一导体和第一导体与基板之间的第一绝缘区域。 电容器还包括第二导体，在第一导体和第二导体之间的第二绝缘区，第三导体和第一导体与第三导体之间的第三绝缘区。 电容器还包括在第一导体和第四导体之间的第四导体和第四绝缘区域。

    Select gate self-aligned patterning in split-gate flash memory cell
    5.
    发明授权
    Select gate self-aligned patterning in split-gate flash memory cell 有权

    公开(公告)号：US10553596B2

    公开(公告)日：2020-02-04

    申请号：US15971159

    申请日：2018-05-04

    Applicant: Texas Instruments Incorporated

    Inventor： Xiangzheng Bo ,  Douglas Tad Grider, III ,  John MacPeak

    IPC: H01L27/11521 ,  H01L29/423 ,  H01L27/11529 ,  G11C16/04

    Abstract: A split-gate flash memory cell (cell) that can be formed by a method including self-aligned patterning for the select gates includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second FG are on the semiconductor surface. A common source/drain is between the first and second FG. A first select gate and a second select gate are on a select gate dielectric layer that is between a first BL source/drain in the semiconductor surface and the first FG and between a second BL source/drain and the second FG, respectively. The first select gate and the second select gate are spacer-shaped.

    Feed-forward bidirectional implanted split-gate flash memory cell
    6.
    发明授权
    Feed-forward bidirectional implanted split-gate flash memory cell 有权
    前馈双向注入分离式闪存单元

    公开(公告)号：US09461060B1

    公开(公告)日：2016-10-04

    申请号：US15098425

    申请日：2016-04-14

    Applicant: Texas Instruments Incorporated

    Inventor： Xiangzheng Bo ,  Douglas Tad Grider

    IPC: G11C16/04 ,  H01L27/115 ,  H01L29/423 ,  H01L29/788 ,  H01L21/265 ,  H01L29/167 ,  H01L29/49 ,  H01L29/66

    CPC classification number: H01L27/11521 ,  G11C16/0425 ,  G11C16/0441 ,  G11C16/26 ,  H01L21/26513 ,  H01L21/26586 ,  H01L21/28273 ,  H01L27/11524 ,  H01L29/0847 ,  H01L29/167 ,  H01L29/42328 ,  H01L29/4916 ,  H01L29/4933 ,  H01L29/66825 ,  H01L29/7883

    Abstract: A split-gate flash memory cell (cell) includes a semiconductor surface. A first control gate (CG) on a first floating gate (FG) and a second CG on a second floating gate (FG) are on the semiconductor surface. A common source or common drain is between the first and second FG. A first select gate and a second select gate on a select gate dielectric layer is between a first BL source or drain (S/D) and the first FG and between a second BL S/D and the second FG, respectively. The first select gate has a first pocket region that has a first doping distribution different from a second doping distribution in a second pocket region associated with the second select gate which reduces a variation in read current (Ir) for the cell between measuring Ir using the first select gate and measuring Ir using the second select gate.

    Abstract translation: 分离式闪存单元（单元）包括半导体表面。 第一浮栅（FG）上的第一控制栅极（CG）和第二浮栅（FG）上的第二CG位于半导体表面上。 共同的源极或共同漏极在第一和第二FG之间。 选择栅极电介质层上的第一选择栅极和第二选择栅极分别在第一BL源极或漏极（S / D）与第一FG之间以及第二BL S / D与第二FG之间。 第一选择栅极具有第一杂质分布区域，其具有与第二选择栅极相关联的第二凹槽区域中的第二掺杂分布不同的第一掺杂分布，其减小了使用第一选择栅极测量Ir之间的单元的读取电流（Ir）的变化 第一选择门并使用第二选择门测量Ir。

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