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    STATIC TIMING SLACKS ANALYSIS AND MODIFICATION
    1.
    发明申请
    STATIC TIMING SLACKS ANALYSIS AND MODIFICATION 有权
    静态时序分析与修改

    公开(公告)号：US20080270962A1

    公开(公告)日：2008-10-30

    申请号：US12138871

    申请日：2008-06-13

    申请人： Thomas B. Chadwick ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wempie

    发明人： Thomas B. Chadwick ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wempie

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

    摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

    Static timing slacks analysis and modification
    2.
    发明授权
    Static timing slacks analysis and modification 有权
    静态定时松散分析和修改

    公开(公告)号：US08015526B2

    公开(公告)日：2011-09-06

    申请号：US12138871

    申请日：2008-06-13

    申请人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

    发明人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

    摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

    Static timing slacks analysis and modification
    3.
    发明授权
    Static timing slacks analysis and modification 有权
    静态定时松散分析和修改

    公开(公告)号：US07404163B2

    公开(公告)日：2008-07-22

    申请号：US11277385

    申请日：2006-03-24

    申请人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

    发明人： Thomas B. Chadwick, Jr. ,  Margaret R. Charlebois ,  David J. Hathaway ,  Jason E. Rotella ,  Douglas W. Stout ,  Ivan L. Wemple

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5031

    摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

    摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。

    Method for dynamically changing the frequency of clock signals
    6.
    发明授权
    Method for dynamically changing the frequency of clock signals 失效
    动态改变时钟信号频率的方法

    公开(公告)号：US07515666B2

    公开(公告)日：2009-04-07

    申请号：US11161335

    申请日：2005-07-29

    申请人： David W. Milton ,  Jason E. Rotella

    发明人： David W. Milton ,  Jason E. Rotella

    IPC分类号： H04L7/00

    CPC分类号： G06F1/12

    摘要： A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

    摘要翻译： 一种用于动态改变时钟信号频率的方法和电路。 该方法包括：使用以第二频率操作的第二时钟信号来检测以第一频率工作的第一时钟信号的边沿; 使用所述第一时钟信号检测所述第二时钟信号的边沿; 检测第一和第二时钟信号的重合边缘; 以及在检测到所述重合边缘时将所述第二频率改变为与所述第二频率不同的第三频率。

    Area efficient, sequential gray code to thermometer code decoder
    7.
    发明授权
    Area efficient, sequential gray code to thermometer code decoder 有权

    公开(公告)号：US06617986B2

    公开(公告)日：2003-09-09

    申请号：US09682449

    申请日：2001-09-04

    申请人： John Connor ,  Patrick R. Hansen ,  Steven Leschuk ,  Jason E. Rotella

    发明人： John Connor ,  Patrick R. Hansen ,  Steven Leschuk ,  Jason E. Rotella

    IPC分类号： H03M704

    CPC分类号： H03M7/16 ,  H03M7/165

    摘要： A Sequential Gray Code to Thermometer Code decoder circuit adapted for area efficient use at each pad of an integrated circuit chip for incrementally adjusting a digitally adjustable resistance for continuous or periodic adjustment of on-chip terminations. The sequential decoder for decoding a Gray code count to a T-bit Thermometer code count is constructed of a plurality (T) of cascaded decoder cells, each cell sensing the state of only one bit of the Gray code count. The decoder cells are cascaded to from decoding-latching stages each stage responsive to an individual one of single-bit changes between consecutive counts in the Gray code. Each stage contains a decoding-latching circuit adapted to detecting and latching the occurrence of one single-bit change in the Gray code.

    Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays
    8.
    发明授权
    Delay-locked-loop (DLL) having symmetrical rising and falling clock edge type delays 有权
    具有对称的上升和下降时钟边缘类型延迟的延迟锁定环（DLL）

    公开(公告)号：US6127866A

    公开(公告)日：2000-10-03

    申请号：US239487

    申请日：1999-01-28

    申请人： Albert M. Chu ,  John A. Fifield ,  Jason E. Rotella ,  Jean-Marc Dortu

    发明人： Albert M. Chu ,  John A. Fifield ,  Jason E. Rotella ,  Jean-Marc Dortu

    IPC分类号： H03K5/15 ,  G11C7/22 ,  H03L7/081 ,  H03L7/095 ,  H03L7/06

    CPC分类号： H03L7/0814 ,  G11C7/22 ,  H03L7/095

    摘要： A circuit and method are provided wherein a receiver receives an input train of pulses. The circuit includes a delay-locked-loop coupled to an output of the receiver. The delay-locked-loop includes a pulse generator responsive to received input train of pulses produced at the output of the receiver for producing first pulses in response to the leading edges of the received input train of pulses and second pulses in response to the trailing edges of received input train of pulses. The leading edge of the first pulse has the same edge type as the leading edge of the second pulse (i.e., the leading edge of the first pulse and the leading edge of the second pulse are either both rising edge types or both falling edges types). The first pulses and the second pulses are combined into a composite input signal comprising the first and second pulses with the leading edge of the first pulse maintaining the same edge type. The delay-locked-loop also includes a variable delay line fed by the composite input signal for producing a composite output train of pulses comprising both the first train of pulses and the second train of pulses after a selected time delay provided by the delay line. The delay-locked-loop is responsive to one of the first train of pulses and the second train of pulses in the composite output train of pulses for selecting the time delay of the variable delay line so as to produce the composite output train of pulses with a predetermined phase relationship to the input train of pulses.

    摘要翻译： 提供一种电路和方法，其中接收器接收输入的脉冲序列。 电路包括耦合到接收器的输出的延迟锁定环路。 延迟锁定环包括响应于在接收器的输出处产生的接收到的输入脉冲序列的脉冲发生器，以响应于所接收的输入脉冲序列的前沿和响应于后沿的第二脉冲而产生第一脉冲 的接收输入脉冲序列。 第一脉冲的前沿具有与第二脉冲的前沿相同的边缘类型（即，第一脉冲的前沿和第二脉冲的前沿都是上升沿类型或两个下降沿类型） 。 第一脉冲和第二脉冲被组合成包括第一和第二脉冲的复合输入信号，其中第一脉冲的前沿保持相同的边缘类型。 延迟锁定环还包括由复合输入信号馈送的可变延迟线，用于在由延迟线提供的选定时间延迟之后产生包括第一脉冲串和第二脉冲串的两个脉冲的复合输出串。 延迟锁定回路响应于复合输出脉冲串中的第一脉冲序列和第二脉冲串中的一个，用于选择可变延迟线的时间延迟，以便产生具有 与输入的脉冲序列的预定相位关系。