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216 条记录 (耗时 0.042 秒)

    Circuit and method for pipelined insertion
    3.
    发明授权
    Circuit and method for pipelined insertion 失效
    流水线插入的电路和方法

    公开(公告)号：US07065602B2

    公开(公告)日：2006-06-20

    申请号：US10604205

    申请日：2003-07-01

    申请人： Robert S. Horton ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Sebastian T. Ventrone

    发明人： Robert S. Horton ,  David W. Milton ,  Clarence R. Ogilvie ,  Paul M. Schanely ,  Sebastian T. Ventrone

    IPC分类号： G06F13/14

    CPC分类号： G06F13/4247 ,  H04L25/14

    摘要： The invention transmits data on an integrated circuit chip by first propagating a first data portion along a first segment of a segmented data line and then propagating the first data portion along a second segment of the segmented data line and simultaneously propagating a second data portion along the first segment of the segmented data line. The invention breaks a single data transmission into such different data portions and later reassembles the different data portions back into the single data transmission after all of the different data portions have been individually transmitted along all portions of the segmented data line

    摘要翻译： 本发明通过首先沿着分段数据线的第一段传播第一数据部分，然后沿着分段数据线的第二段传播第一数据部分并同时沿第二数据部分传播第二数据部分 分段数据线的第一段。 本发明将单个数据传输中断到这样的不同数据部分，并且随后将所有不同数据部分已经沿着分段数据线的所有部分单独发送，将不同的数据部分重新组合成单​​个数据传输

    INTEGRATED CIRCUIT CHIP INCORPORATING EMBEDDED THERMAL RADIATORS FOR LOCALIZED, ON-DEMAND, HEATING AND A SYSTEM AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT CHIP
    5.
    发明申请
    INTEGRATED CIRCUIT CHIP INCORPORATING EMBEDDED THERMAL RADIATORS FOR LOCALIZED, ON-DEMAND, HEATING AND A SYSTEM AND METHOD FOR DESIGNING SUCH AN INTEGRATED CIRCUIT CHIP 失效
    集成电路芯片，用于本地化，点燃，加热和系统的嵌入式热分解器以及用于设计这种集成电路芯片的方法

    公开(公告)号：US20120168416A1

    公开(公告)日：2012-07-05

    申请号：US12984638

    申请日：2011-01-05

    申请人： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

    发明人： Richard S. Graf ,  Keishi Okamoto ,  Faraydon Pakbaz ,  Jack R. Smith ,  Sebastian T. Ventrone

    IPC分类号： H05B3/00 ,  G06F17/50

    CPC分类号： H05B1/0227 ,  G05D23/1934

    摘要： Disclosed are embodiments of an integrated circuit chip designed for reliability at low ambient temperatures. The chip substrate can be divided into zones, including at least one temperature-sensitive zone (TSZ) that contains one or more temperature-sensitive circuits. Temperature sensor(s) can be positioned in the semiconductor substrate adjacent to the TSZ. Thermal radiator(s) can be embedded in a metal wiring layer and aligned above the TSZ. The temperature sensor(s) can be operatively connected to the thermal radiator(s) and can trigger operation of the thermal radiator(s) when the temperature in the TSZ is below a predetermined threshold temperature. Additionally, an on-chip power control system can be operatively connected to the thermal radiator(s) so that operation of the thermal radiator(s) is only triggered when a circuit within the TSZ is about to be powered up. Also disclosed are associated embodiments of a system and method for designing such an integrated circuit chip.

    摘要翻译： 公开了设计用于在低环境温度下可靠性的集成电路芯片的实施例。 芯片基板可以分为包括至少一个包含一个或多个温度敏感电路的至少一个温度敏感区（TSZ）的区域。 温度传感器可以位于与TSZ相邻的半导体衬底中。 热辐射器可以嵌入在金属布线层中，并在TSZ上方对齐。 温度传感器可以可操作地连接到散热器，并且当TSZ中的温度低于预定阈值温度时，可以触发热辐射器的操作。 此外，片上功率控制系统可以可操作地连接到散热器，使得热辐射器的操作仅在TSZ内的电路即将被加电时触发。 还公开了用于设计这种集成电路芯片的系统和方法的相关实施例。

    Processor pipeline architecture logic state retention systems and methods
    6.
    发明授权
    Processor pipeline architecture logic state retention systems and methods 有权
    处理器管道架构逻辑状态保留系统和方法

    公开(公告)号：US07937560B2

    公开(公告)日：2011-05-03

    申请号：US12121292

    申请日：2008-05-15

    申请人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kerry Bernstein ,  Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Christopher B. Reynolds ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F15/76 ,  G06F1/00

    CPC分类号： G06F9/3867 ,  G06F1/32 ,  G06F1/3287 ,  G06F11/1407 ,  G06F11/1441 ,  Y02D10/171

    摘要： A solution for retaining a logic state of a processor pipeline architecture are disclosed. A comparator is positioned between two stages of the processor pipeline architecture. A storage capacitor is coupled between a storage node of the comparator and a ground to store an output of the early one of the two stages. A reference logic is provided, which has the same value as the output of the early stage. A logic storing and dividing device is coupled between the reference logic and a reference node of the comparator to generate a logic at the reference node, which is a fraction of the reference logic, and to retain a logic state of the information stored on the storage capacitor. Further mechanisms are provided to determine validity of data stored in the logic storing and dividing device.

    摘要翻译： 公开了一种用于保留处理器流水线架构的逻辑状态的解决方案。 比较器位于处理器流水线架构的两个阶段之间。 存储电容器耦合在比较器的存储节点和地之间以存储两个阶段的早期阶段的输出。 提供了与早期输出值相同的参考逻辑。 逻辑存储和分配装置耦合在参考逻辑和比较器的参考节点之间，以便在参考节点产生逻辑，该参考节点是参考逻辑的一小部分，并且保留存储在存储器上的信息的逻辑状态 电容器。 提供进一步的机制来确定存储在逻辑存储和分配装置中的数据的有效性。

    Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly
    7.
    发明授权
    Structure for a system and method of predicting power events in an intermittent power environment and dispatching computational operations of an integrated circuit accordingly 有权
    一种用于预测间歇电力环境中的电力事件并且相应地调度集成电路的计算操作的系统和方法的结构

    公开(公告)号：US07895459B2

    公开(公告)日：2011-02-22

    申请号：US11938899

    申请日：2007-11-13

    申请人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    发明人： Kenneth J. Goodnow ,  Clarence R. Ogilvie ,  Sebastian T. Ventrone ,  Keith R. Williams

    IPC分类号： G06F1/00

    CPC分类号： G06F1/3203 ,  G06F1/3287 ,  Y02D10/171

    摘要： A design structure for a system and method of predicting power events in intermittent power environments and dispatching computational operations of an integrated circuit accordingly. A power management prediction system includes a controller executing a prediction algorithm, an arrangement of computation circuitry, a non-volatile storage device containing a power requirements log and a power history log, a clock generator, an intermittent power source, and a power monitor circuit. A method of predicting intermittent power events and dispatching computational operations includes: storing power requirements of each computational operation, monitoring the intermittent power source to generate a history log, predicting a subsequent power event based on the history log, retrieving actual power requirements of one or more computational operations, comparing the predicted power event with actual power requirements, determining whether actual power requirements are satisfied, dispatching one or more computational operations that correspond to one or more actual power events, or performing an error recovery operation.

    摘要翻译： 一种用于系统的设计结构以及在间歇电力环境中预测电力事件并相应地调度集成电路的计算操作的方法。 功率管理预测系统包括执行预测算法的控制器，计算电路的布置，包含电力需求日志和电力历史记录的非易失性存储装置，时钟发生器，间歇电源和功率监视电路 。 一种预测间歇功率事件和调度计算操作的方法包括：存储每个计算操作的功率需求，监测间歇电源以生成历史日志，根据历史日志预测后续功率事件，检索一个或者 更多的计算操作，将预测功率事件与实际功率需求进行比较，确定是否满足实际功率需求，调度与一个或多个实际功率事件相对应的一个或多个计算操作，或执行错误恢复操作。

    SYSTEM AND METHOD OF MASKING ELECTROMAGNETIC INTERFERENCE (EMI) EMISSIONS OF A CIRCUIT
    8.
    发明申请
    SYSTEM AND METHOD OF MASKING ELECTROMAGNETIC INTERFERENCE (EMI) EMISSIONS OF A CIRCUIT 有权
    屏蔽电路电磁干扰（EMI）排放的系统和方法

    公开(公告)号：US20110019819A1

    公开(公告)日：2011-01-27

    申请号：US12507481

    申请日：2009-07-22

    申请人： Kerry Bernstein ,  Sebastian T. Ventrone

    发明人： Kerry Bernstein ,  Sebastian T. Ventrone

    IPC分类号： H04K1/02

    CPC分类号： H04K3/825 ,  H04K3/42

    摘要： A system is provided for securing information residing on a circuit (e.g., processor). In particular, a system and method is provided for masking electromagnetic interference (EMI) emissions emitting from a circuit using a random noise generator in combination with a low noise amplifier and antenna. The random number generator matches a frequency of a circuit to be protected, and generates a random signal to be superimposed on data. The low noise amplifier receives the random signal from the random number generator, and an antenna receives the random signal from the low noise amplifier and transmits the random signal to mask the data of the circuit to be protected.

    摘要翻译： 提供了用于保护驻留在电路（例如，处理器）上的信息的系统。 特别地，提供了一种用于屏蔽使用随机噪声发生器与低噪声放大器和天线组合的从电路发射的电磁干扰（EMI）发射的系统和方法。 随机数发生器匹配要保护的电路的频率，并产生要叠加在数据上的随机信号。 低噪声放大器从随机数发生器接收随机信号，并且天线从低噪声放大器接收随机信号，并发送随机信号以掩蔽要被保护的电路的数据。

    Design structure for dynamically selecting compiled instructions
    9.
    发明授权
    Design structure for dynamically selecting compiled instructions 有权
    动态选择编译指令的设计结构

    公开(公告)号：US07865862B2

    公开(公告)日：2011-01-04

    申请号：US11937106

    申请日：2007-11-08

    申请人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

    发明人： Deanna J. Chou ,  Jesse E. Craig ,  John Sargis, Jr. ,  Daneyand J. Singley ,  Sebastian T. Ventrone

    IPC分类号： G06F17/50

    CPC分类号： G06F9/3836 ,  G06F9/3885

    摘要： A design structure embodied in a machine readable medium used in a design process includes an apparatus for dynamically selecting compiled instructions for execution, the apparatus including an input for receiving static instructions for execution on a first execution unit and receiving dynamic instructions for execution on a second execution unit; and an instruction selection element adapted to evaluate throughput performance of the static instructions and dynamic instructions based on current states of the execution units and select the static instructions or the dynamic instructions for execution at runtime on the first execution unit or the second execution unit, respectively, based on the throughput performance of the instructions.

    摘要翻译： 体现在设计过程中使用的机器可读介质中的设计结构包括用于动态选择编译指令进行执行的装置，该装置包括用于接收用于在第一执行单元上执行的静态指令的输入，以及在第二执行单元上接收用于执行的动态指令 执行单位 以及指令选择元件，其适于基于所述执行单元的当前状态来评估所述静态指令和动态指令的吞吐量性能，并分别在所述第一执行单元或所述第二执行单元上的运行时选择所述静态指令或用于执行的所述动态指令 ，基于指令的吞吐量性能。