公开(公告)号：US11614486B2

公开(公告)日：2023-03-28

申请号：US17406084

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Tsou ,  Chang-Ting Lo

IPC: G01R31/3185 ,  G01R31/319 ,  G01R22/00

Abstract: A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

公开(公告)号：US20230020783A1

公开(公告)日：2023-01-19

申请号：US17406084

申请日：2021-08-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Wei Tsou ,  Chang-Ting Lo

IPC: G01R31/3185 ,  G01R31/319

Abstract: A testkey includes two switching circuits and two compensation circuits. The first switching circuit transmits a test signal to a first DUT when the first DUT is being tested and functions as high impedance when the first DUT is not being tested. The second switching circuit transmits the test signal to a second DUT when the second DUT is being tested and functions as high impedance when the second DUT is not being tested. When the first DUT is not being tested and the second DUT is being tested, the first compensation circuit provides first compensation current for reducing the leakage current of the first switching circuit. When the first DUT is being tested and the second DUT is not being tested, the second compensation circuit provides second compensation current for reducing the leakage current of the second switching circuit.

公开(公告)号：US10762951B1

公开(公告)日：2020-09-01

申请号：US16455783

申请日：2019-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Tsai ,  Tsan-Tang Chen ,  Chung-Cheng Tsai ,  Yen-Hsueh Huang ,  Chang-Ting Lo ,  Chun-Yen Tseng ,  Yu-Tse Kuo

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.