公开(公告)号：US10861549B1

公开(公告)日：2020-12-08

申请号：US16503617

申请日：2019-07-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai ,  Hsin-Chih Yu ,  Shu-Ru Wang

IPC: G11C15/00 ,  G11C15/04 ,  H01L27/11

Abstract: A ternary content addressable memory unit includes a first inverter, a second inverter, a third inverter, a fourth inverter, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor. The first inverter includes an input terminal, and an output terminal coupled to a first node. The second inverter includes an input terminal coupled to the first node and an output terminal coupled to the input terminal of the first inverter. The third inverter includes an input terminal coupled to a second node and an output terminal. The fourth inverter includes an input terminal coupled to the output terminal of the third inverter and an output terminal coupled to the second node.

公开(公告)号：US10978122B1

公开(公告)日：2021-04-13

申请号：US16796953

申请日：2020-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Yu-Tse Kuo ,  Chang-Hung Chen ,  Shu-Ru Wang ,  Ya-Lan Chiou ,  Chun-Hsien Huang ,  Chih-Wei Tsai ,  Hsin-Chih Yu ,  Yi-Ting Wu ,  Cheng-Tung Huang ,  Jen-Yu Wang ,  Jhen-Siang Wu ,  Po-Chun Yang ,  Yung-Ching Hsieh ,  Jian-Jhong Chen ,  Bo-Chang Li

IPC: G11C11/00 ,  G11C11/16 ,  H01L27/22

Abstract: A memory includes (n−1) non-volatile cells, (n−1) bit lines and a current driving circuit. Each of the (n−1) non-volatile cells includes a first terminal and a second terminal. An ith bit line of the (n−1) bit lines is coupled to a first terminal of an ith non-volatile cell of the (n−1) non-volatile cells. The current driving circuit includes n first transistors coupled to the (n−1) non-volatile cells.

公开(公告)号：US10762951B1

公开(公告)日：2020-09-01

申请号：US16455783

申请日：2019-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Tsai ,  Tsan-Tang Chen ,  Chung-Cheng Tsai ,  Yen-Hsueh Huang ,  Chang-Ting Lo ,  Chun-Yen Tseng ,  Yu-Tse Kuo

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

公开(公告)号：US10020049B1

公开(公告)日：2018-07-10

申请号：US15413436

申请日：2017-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai

IPC: G11C11/419 ,  G11C11/418

Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.

公开(公告)号：US20180190344A1

公开(公告)日：2018-07-05

申请号：US15413436

申请日：2017-01-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun-Yen Tseng ,  Ching-Cheng Lung ,  Yu-Tse Kuo ,  Chun-Hsien Huang ,  Chih-Wei Tsai

IPC: G11C11/419 ,  G11C11/418

CPC classification number: G11C11/419 ,  G11C11/412 ,  G11C11/418

Abstract: The present invention provides a six transistor static random-access memory (6T-SRAM) cell, the 6T-SRAM cell includes a first inverter comprising a first pull-up transistor and a first pull-down transistor, and a first storage node, a second inverter comprising a second pull-up transistor, a second pull-down transistor, and a second storage node, wherein the first storage node is coupled to gates of the second pull-up transistor and the second pull-down transistor, a switch transistor configured to couple the second storage node to gates of the first pull-up transistor and the first pull-down transistor, and an access transistor coupled to gates of the first pull-up transistor and the first pull-down transistor.