公开(公告)号：US20190043587A1

公开(公告)日：2019-02-07

申请号：US15710851

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC: G11C16/24 ,  G11C7/18 ,  G06F17/50 ,  H01L27/02

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

公开(公告)号：US10777260B1

公开(公告)日：2020-09-15

申请号：US16655220

申请日：2019-10-16

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zih-Yu Chiu ,  Hsin-Wen Chen ,  Ya-Nan Mou ,  Yuan-Hui Chen ,  Chung-Cheng Tsai

IPC: G11C11/00 ,  G11C11/412 ,  G11C11/419 ,  H01L27/11

Abstract: An SRAM cell includes two inverters and three transistors. The first inverter includes a first end coupled to a first storage node and a second end coupled to a second storage node. The second inverter includes a first end coupled to the second storage node and a second end coupled to the first storage node. The first transistor includes a first end coupled to the first storage node, a second end and a control end. The second transistor includes a first end coupled to the second end of the first transistor, a second end coupled to a first bit line, and a control end. The third transistor includes a first end coupled between the second end of the first transistor and the first end of the second transistor, a second end, and a control end coupled to the first storage node.

公开(公告)号：US10762951B1

公开(公告)日：2020-09-01

申请号：US16455783

申请日：2019-06-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Tsai ,  Tsan-Tang Chen ,  Chung-Cheng Tsai ,  Yen-Hsueh Huang ,  Chang-Ting Lo ,  Chun-Yen Tseng ,  Yu-Tse Kuo

IPC: G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An SRAM device includes a memory cell and a keeper circuit. The memory cell is formed in an active area and coupled to a first bit line and a second bit line. The keeper circuit is formed in the active area and configured to charge the second bit line when the first bit line is at a first voltage level and the second bit line is at a second voltage level or charge the first bit line when the second bit line is at the first voltage level and the first bit line is at the second voltage level, wherein the second voltage level is higher than the first voltage level.

公开(公告)号：US10580499B2

公开(公告)日：2020-03-03

申请号：US15710851

申请日：2017-09-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Chi-Hsiu Hsu ,  Chung-Hao Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai

IPC: G11C16/24 ,  G11C7/18 ,  H01L27/112 ,  H01L27/02 ,  G11C17/12 ,  G06F17/50 ,  G11C7/02

Abstract: A read only memory (ROM) is provided in the present invention, which includes a plurality of bit lines extending in a first direction, a plurality of source lines extending in parallel to the plurality of bit lines, and a plurality of word lines extending in a second direction perpendicular to the first direction. Each two ROM cells share an active area and are electrically coupled to one of the plurality of source lines by a common source line contact.

公开(公告)号：US20150095728A1

公开(公告)日：2015-04-02

申请号：US14040752

申请日：2013-09-30

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsin-Pang Lu ,  Hsi-Wen Chen ,  Ya-Nan Mou ,  Chung-Cheng Tsai ,  Hsiao-Chieh Sung ,  Yin-Ju Hsiao

IPC: G11C29/00

CPC classification number: G11C29/04 ,  G11C29/006

Abstract: A testing method for non-volatile memory includes writing a first set of data to a set of addresses in a non-volatile memory, reading a second set of data from the set of addresses, and writing the first set of data to the set of addresses again if the first set of data and the second set of data are not identical and number of times for writing the first set of data to the set of addresses is smaller than a predetermined number.

Abstract translation: 用于非易失性存储器的测试方法包括将第一组数据写入非易失性存储器中的一组地址，从该地址集中读取第二组数据，以及将第一组数据写入到 如果第一组数据和第二组数据不相同，并且将第一组数据写入地址集合的次数小于预定数量，则再次寻址。

公开(公告)号：US08724404B2

公开(公告)日：2014-05-13

申请号：US13652422

申请日：2012-10-15

Applicant: United Microelectronics Corp.

Inventor： Shi-Wen Chen ,  Hsin-Pang Lu ,  Chung-Cheng Tsai ,  Ya-Nan Mou

IPC: G11C5/14 ,  G11C7/10 ,  G11C7/06 ,  G11C11/4074 ,  G11C7/00

CPC classification number: G11C5/147 ,  G11C7/00 ,  G11C7/08 ,  G11C7/10 ,  G11C8/08 ,  G11C11/4074 ,  G11C16/30 ,  G11C29/021

Abstract: A supply voltage generation circuit includes a comparison unit, a voltage level control unit and a voltage regulator circuit. The comparison unit is configured to compare input data and output data of a memory array to each other and thereby generating a comparison result, wherein the output data are storage data stored in a plurality of memory units of the memory array processed by a program operation according to the input data, and the comparison result indicates the number of different bits existing between the output data and the input data. The voltage level control unit is configured to generate a control signal according to the comparison result. The voltage regulator circuit is configured to provide a supply voltage for the memory array and adjust the value of the supply voltage according to the control signal. A memory and an operation method of a supply generation circuit used for a memory array are also provided.

Abstract translation: 电源电压产生电路包括比较单元，电压电平控制单元和电压调节器电路。 比较单元被配置为将存储器阵列的输入数据和输出数据彼此进行比较，从而生成比较结果，其中输出数据是存储在由程序操作处理的存储器阵列的多个存储器单元中的存储数据， 并且比较结果表示存在于输出数据和输入数据之间的不同位的数量。 电压电平控制单元被配置为根据比较结果产生控制信号。 电压调节器电路被配置为为存储器阵列提供电源电压，并根据控制信号调节电源电压的值。 还提供了用于存储器阵列的供应生成电路的存储器和操作方法。