公开(公告)号：US11545484B2

公开(公告)日：2023-01-03

申请号：US17150960

申请日：2021-01-15

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392 ,  G06F119/18

Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

公开(公告)号：US20210134790A1

公开(公告)日：2021-05-06

申请号：US17150960

申请日：2021-01-15

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392

Abstract: A design method of a dummy pattern layout including the following steps is provided. An integrated circuit layout design including resistor elements is obtained via a computer. The locations of dummy conductive structures are configured, wherein the dummy conductive structures are aligned with the resistor elements. The locations of dummy support patterns are configured, wherein each of the dummy support patterns is configured between two adjacent dummy conductive structures, and each of the dummy conductive structures is equidistant from the dummy support patterns on both sides.

公开(公告)号：US20230260827A1

公开(公告)日：2023-08-17

申请号：US17687692

申请日：2022-03-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Che-Hao Kuo ,  Ssu-Yin Liu ,  Ching-Hua Yeh ,  I-Hsin Sung

IPC: H01L21/762 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/3115 ,  H01L23/00

CPC classification number: H01L21/76224 ,  H01L21/32139 ,  H01L21/31144 ,  H01L21/31155 ,  H01L23/573

Abstract: A method for fabricating a physically unclonable function (PUF) device includes the steps of first defining a PUF cell region on a substrate and then performing a process to form a defect on the PUF cell region. Preferably, the formation of the defect could be accomplished by forming a shallow trench isolation (STI) on the substrate, forming a gate material layer on the substrate and the STI, patterning the gate material layer to form a first gate material layer and a second gate material layer, and then forming an epitaxial layer between and connecting the first gate material layer and the second gate material layer.

公开(公告)号：US20240006345A1

公开(公告)日：2024-01-04

申请号：US17874299

申请日：2022-07-27

Applicant: United Microelectronics Corp.

Inventor： Po Hsien Chen ,  Ping-Chia Shih ,  Che Hao Kuo ,  Chia-Min Hung ,  Ching-Hua Yeh ,  Wan-Chun Liao

IPC: H01L23/00 ,  H04L9/32 ,  H01L29/06

CPC classification number: H01L23/57 ,  H04L9/3278 ,  H01L29/0649

Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

公开(公告)号：US10964689B2

公开(公告)日：2021-03-30

申请号：US15705026

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/528 ,  H01L29/66 ,  H01L23/532 ,  H01L49/02 ,  H01L23/522 ,  G06F30/39 ,  G06F30/392 ,  G06F119/18

Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.

公开(公告)号：US20190057962A1

公开(公告)日：2019-02-21

申请号：US15705026

申请日：2017-09-14

Applicant: United Microelectronics Corp.

Inventor： Jui-Fa Lu ,  Chien-Nan Lin ,  Ching-Hua Yeh

IPC: H01L27/06 ,  H01L29/06 ,  H01L29/49 ,  H01L23/532 ,  H01L23/528 ,  H01L29/66 ,  G06F17/50

Abstract: A semiconductor structure including a substrate, dummy conductive structures, and resistor elements is provided. The substrate includes a resistor region and has isolation structures and dummy support patterns located in the resistor region. Each of the isolation structures is located between two adjacent dummy support patterns. Each of the dummy conductive structures is disposed on each of the isolation structures and equidistant from the dummy support patterns on both sides. The resistor elements are disposed above the dummy conductive structures and aligned with the dummy conductive structures.