公开(公告)号：US10199385B1

公开(公告)日：2019-02-05

申请号：US15665437

申请日：2017-08-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kuo-Lung Li ,  Ping-Chia Shih ,  Wen-Peng Hsu ,  Chia-Wen Wang ,  Meng-Chun Chen ,  Chih-Hao Pan

IPC: H01L27/115 ,  H01L27/11568 ,  H01L29/423 ,  H01L29/792 ,  H01L21/28 ,  H01L29/66

Abstract: A non-volatile memory device includes a semiconductor substrate, a control gate electrode, a first oxide-nitride-oxide (ONO) structure, a selecting gate electrode, a second ONO structure, and a spacer structure. The control gate electrode and the selecting gate electrode are disposed on the semiconductor substrate. The first ONO structure is disposed between the control gate electrode and the semiconductor substrate. The second ONO structure is disposed between the control gate electrode and the selecting gate electrode in a first direction. The spacer structure is disposed between the control gate electrode and the second ONO structure in the first direction. A distance between the control gate electrode and the selecting gate electrode in the first direction is smaller than or equal to a sum of a width of the second ONO structure and a width of the spacer structure in the first direction.

公开(公告)号：US20190013324A1

公开(公告)日：2019-01-10

申请号：US15641560

申请日：2017-07-05

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih ,  Chun-Yao Wang ,  Ming-Hua Tsai ,  Wan-Chun Liao

IPC: H01L27/11573 ,  H01L27/11568 ,  H01L21/266 ,  H01L21/28

Abstract: A method for fabricating a semiconductor integrated circuit (IC) having a SONOS memory device and a logic/analog device requiring different gate oxide layers comprises steps as follows: A substrate having a high voltage region, a memory region and a logic/analog is firstly provided. Next, a first gate oxide layer is formed on the high voltage region, the memory region and the logic/analog. The first gate oxide layer is then patterned to expose the logic/analog region and to define a first channel area and a second channel area respectively on the memory region and the high voltage region. Subsequently, a silicon oxide-silicon nitride-silicon oxide (ONO) structure is formed on the first channel area. A second gate oxide layer is then formed on the logic/analog and patterned to define a third channel area.

公开(公告)号：US09966382B2

公开(公告)日：2018-05-08

申请号：US15238574

申请日：2016-08-16

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L29/66 ,  H01L21/28 ,  H01L27/11543 ,  H01L27/11563

CPC classification number: H01L27/1157 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11543 ,  H01L27/11563 ,  H01L27/11573 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/7881 ,  H01L29/792

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US09397202B1

公开(公告)日：2016-07-19

申请号：US15077937

申请日：2016-03-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Wan-Fang Chung ,  Yu-Chun Chang ,  Je-Yi Su

IPC: H01L21/336 ,  H01L29/66 ,  H01L21/28 ,  H01L27/115 ,  H01L21/02 ,  H01L21/033

CPC classification number: H01L29/66833 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02271 ,  H01L21/0332 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/42348 ,  H01L29/792 ,  H01L29/7923

Abstract: A method for fabricating semiconductor device is disclosed. Preferably, two hard masks are utilized to define the width of the first gate (may serve for a control gate) and the width of the second gate (may serve for a select gate). The widths are thus well controlled. For example, in an embodiment, the width of the select gate may be adjusted in advance as desired, and the select gate is protected by the second hard mask during an etch process, so as to obtain a select gate which upper portion has an appropriate width. Accordingly the semiconductor device would still have an excellent performance upon miniaturization.

Abstract translation: 公开了半导体器件的制造方法。 优选地，使用两个硬掩模来限定第一栅极的宽度（可用于控制栅极）和第二栅极的宽度（可用于选择栅极）。 因此，宽度被很好地控制。 例如，在实施例中，可以根据需要预先调整选择栅极的宽度，并且在蚀刻工艺期间选择栅极被第二硬掩模保护，以便获得选择栅极，其上部具有适当的 宽度。 因此，半导体器件在小型化时仍然具有优异的性能。

公开(公告)号：US09330923B1

公开(公告)日：2016-05-03

申请号：US14576227

申请日：2014-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ping-Chia Shih

IPC: H01L21/336 ,  H01L21/28 ,  H01L27/115

CPC classification number: H01L27/11521

Abstract: A semiconductor process includes the steps of providing a semiconductor substrate with a logic region and a memory region, defining memory gates on the memory region, forming a conformal spacer layer on the memory gates and the semiconductor substrate, and performing an etch process on the conformal spacer layer, such that the conformal spacer layer on sidewalls of the memory gates transforms into spacers, and the conformal spacer layer between the memory gates transforms into a concave block covering the semiconductor substrate between the memory gates.

Abstract translation: 半导体工艺包括以下步骤：为半导体衬底提供逻辑区域和存储区域，在存储器区域上限定存储器栅极，在存储器栅极和半导体衬底上形成保形隔离层，并对保形膜进行蚀刻工艺 间隔层，使得存储器栅极的侧壁上的共形间隔层转变成间隔物，并且存储器栅之间的共形间隔层转变成覆盖存储器栅极之间的半导体衬底的凹块。

公开(公告)号：US09129852B1

公开(公告)日：2015-09-08

申请号：US14457107

申请日：2014-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hsiang-Chen Lee ,  Shao-Nung Huang ,  Wei-Pin Huang ,  Kuo-Lung Li ,  Ling-Hsiu Chou ,  Ping-Chia Shih

IPC: H01L29/788 ,  H01L27/115

CPC classification number: H01L27/115 ,  H01L27/11524 ,  H01L27/1157

Abstract: A method for fabricating a non-volatile memory semiconductor device is disclosed. The method includes the steps of providing a substrate; forming a gate pattern on the substrate, wherein the gate pattern comprises a first polysilicon layer on the substrate, an oxide-nitride-oxide (ONO) stack on the first polysilicon layer, and a second polysilicon layer on the ONO stack; forming an oxide layer on the top surface and sidewall of the gate pattern; performing a first etching process to remove part of the oxide layer; and performing a second etching process to completely remove the remaining oxide layer.

Abstract translation: 公开了一种用于制造非易失性存储器半导体器件的方法。 该方法包括提供基板的步骤; 在所述衬底上形成栅极图案，其中所述栅极图案包括所述衬底上的第一多晶硅层，所述第一多晶硅层上的氧化物 - 氧化物 - 氧化物（ONO）堆叠以及所述ONO堆叠上的第二多晶硅层; 在栅极图案的顶表面和侧壁上形成氧化物层; 执行第一蚀刻工艺以去除部分氧化物层; 并执行第二蚀刻处理以完全去除剩余的氧化物层。

公开(公告)号：US11282799B2

公开(公告)日：2022-03-22

申请号：US16741756

申请日：2020-01-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Lin Wang ,  Ping-Chia Shih ,  Ming-Che Tsai ,  Kuei-Ya Chuang ,  Yi-Chun Teng ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L23/00 ,  H01L27/088 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/522

Abstract: A device for generating a security key includes a substrate, semiconductor units, contact structures, and defects. The semiconductor units are disposed on the substrate. The contact structures are disposed on and connected with the semiconductor units. The defects are disposed in at least a part of the contact structures randomly. A manufacturing method of a device for generating a security key includes the following steps. First semiconductor units are formed on a substrate. First contact structures are formed on the first semiconductor units. The first contact structures are connected with the first semiconductor units, and defects are formed in at least a part of the first contact structures randomly.

公开(公告)号：US10720440B2

公开(公告)日：2020-07-21

申请号：US15927914

申请日：2018-03-21

Applicant: United Microelectronics Corp.

Inventor： Chia-Wen Wang ,  Hsiang-Chen Lee ,  Wen-Peng Hsu ,  Kuo-Lung Li ,  Meng-Chun Chen ,  Zi-Jun Liu ,  Ping-Chia Shih

IPC: H01L27/115 ,  H01L29/66 ,  H01L27/1157 ,  H01L29/792 ,  H01L29/78 ,  H01L27/11573 ,  H01L27/11543 ,  H01L27/11563 ,  H01L21/28 ,  H01L29/788

Abstract: A method for fabricating a semiconductor structure is shown. A first gate of a first device and a second gate of a second device are formed over a semiconductor substrate. First LDD regions are formed in the substrate beside the first gate using the first gate as a mask. A conformal layer is formed covering the first gate, the second gate and the substrate, wherein the conformal layer has sidewall portions on sidewalls of the second gate. Second LDD regions are formed in the substrate beside the second gate using the second gate and the sidewall portions of the conformal layer as a mask.

公开(公告)号：US20180182900A1

公开(公告)日：2018-06-28

申请号：US15437740

申请日：2017-02-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ya-Sheng Feng ,  Chi-Cheng Huang ,  Ping-Chia Shih ,  Hung-Wei Lin ,  Yu-Chun Chen ,  Ling-Hsiu Chou ,  An-Hsiu Cheng

IPC: H01L29/792 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/792 ,  H01L21/823462 ,  H01L29/4234 ,  H01L29/42368 ,  H01L29/66833

Abstract: A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes a semiconductor substrate having a tunneling well, a tunneling oxide layer, a charge storage layer and a control gate. The tunneling oxide layer is disposed on the tunneling well. The tunneling oxide layer includes a first tunneling oxide segment having a first thickness, a second tunneling oxide segment having a second thickness, and a third tunneling oxide segment having a third thickness, and the first thickness, the second thickness and the third thickness are different from each other. The charge storage layer is disposed on the tunneling oxide layer, and the control gate is disposed on the charge storage layer.

公开(公告)号：US20170200729A1

公开(公告)日：2017-07-13

申请号：US14993101

申请日：2016-01-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tseng-Fang Dai ,  Ping-Chia Shih ,  Chi-Cheng Huang ,  Kun-I Chou ,  Hung-Wei Lin ,  Ching-Wen Yang

IPC: H01L27/115 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/518 ,  H01L27/11582 ,  H01L28/00 ,  H01L29/513 ,  H01L29/66545

Abstract: An integrated circuit process includes the following steps. A substrate including a flash cell area and a logic area is provided. A first sacrificial gate on the substrate of the flash cell area and a second sacrificial gate on the substrate of the logic area are formed, and a dielectric layer covers the substrate beside the first sacrificial gate and the second sacrificial gate. The first sacrificial gate is removed to forma first recess in the dielectric layer. An oxide/nitride/oxide layer is formed to conformally cover surfaces of the first recess. An integrated circuit formed by said integrated circuit process is also provided.