公开(公告)号：US20170084739A1

公开(公告)日：2017-03-23

申请号：US14886108

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Chia-Min Hung

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H01L21/441 ,  H01L21/4763 ,  H01L21/471 ,  H01L21/4757 ,  H01L29/24 ,  H01L29/66

CPC classification number: H01L29/7823 ,  H01L21/441 ,  H01L21/471 ,  H01L21/47573 ,  H01L21/4763 ,  H01L21/47635 ,  H01L29/0611 ,  H01L29/0653 ,  H01L29/24 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/66689 ,  H01L29/66969 ,  H01L29/7816

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.

公开(公告)号：US09391196B1

公开(公告)日：2016-07-12

申请号：US14805474

申请日：2015-07-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/06 ,  H01L29/08

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A high-voltage metal-oxide-semiconductor (HV MOS) transistor device and a manufacturing method thereof are provided. The HV MOS transistor device includes a semiconductor substrate, a gate structure, a first sub-gate structure, and a drain region. The gate structure is disposed on the semiconductor substrate. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the semiconductor substrate, the first sub-gate structure is separated from the gate structure, and the first sub-gate structure is disposed on the first region of the semiconductor substrate. The drain region is disposed in the first region of the semiconductor substrate. The drain region is electrically connected to the first sub-gate structure via a first contact structure disposed on the drain region and the first sub-gate structure.

Abstract translation: 提供高压金属氧化物半导体（HV MOS）晶体管器件及其制造方法。 HV MOS晶体管器件包括半导体衬底，栅极结构，第一子栅极结构和漏极区域。 栅极结构设置在半导体衬底上。 半导体衬底具有分别设置在栅极结构的两个相对侧上的第一区域和第二区域。 第一子栅极结构设置在半导体衬底上，第一子栅极结构与栅极结构分离，第一子栅极结构设置在半导体衬底的第一区域上。 漏极区域设置在半导体衬底的第一区域中。 漏极区域经由设置在漏极区域和第一子栅极结构上的第一接触结构电连接到第一子栅极结构。

公开(公告)号：US09722072B2

公开(公告)日：2017-08-01

申请号：US15173728

申请日：2016-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/66 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

公开(公告)号：US20170025531A1

公开(公告)日：2017-01-26

申请号：US15173728

申请日：2016-06-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Kai-Kuen Chang ,  Chia-Min Hung ,  Shih-Yin Hsiao

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/10 ,  H01L29/66

CPC classification number: H01L29/7816 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7833 ,  H01L29/7834 ,  H01L29/7835

Abstract: A manufacturing method of a high-voltage metal-oxide-semiconductor (HV MOS) transistor device is provided. The manufacturing method includes the following steps. A semiconductor substrate is provided. A patterned conductive structure is formed on the semiconductor substrate. The patterned conductive structure includes a gate structure and a first sub-gate structure. The semiconductor substrate has a first region and a second region respectively disposed on two opposite sides of the gate structure. The first sub-gate structure is disposed on the first region of the semiconductor substrate. The first sub-gate structure is separated from the gate structure. A drain region is formed in the first region of the semiconductor substrate. A first contact structure is formed on the drain region and the first sub-gate structure. The drain region is electrically connected to the first sub-gate structure via the first contact structure.

Abstract translation: 提供了高压金属氧化物半导体（HV MOS）晶体管器件的制造方法。 该制造方法包括以下步骤。 提供半导体衬底。 在半导体衬底上形成有图案的导电结构。 图案化导电结构包括栅极结构和第一子栅极结构。 半导体衬底具有分别设置在栅极结构的两个相对侧上的第一区域和第二区域。 第一子栅极结构设置在半导体衬底的第一区域上。 第一子栅极结构与栅极结构分离。 漏极区域形成在半导体衬底的第一区域中。 在漏极区域和第一子栅极结构上形成第一接触结构。 漏极区域经由第一接触结构电连接到第一子栅极结构。

公开(公告)号：US11758720B2

公开(公告)日：2023-09-12

申请号：US18077183

申请日：2022-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H10B41/30 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

CPC classification number: H10B41/30 ,  H01L29/40114 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7881

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US11552088B2

公开(公告)日：2023-01-10

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L29/788

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US20240006345A1

公开(公告)日：2024-01-04

申请号：US17874299

申请日：2022-07-27

Applicant: United Microelectronics Corp.

Inventor： Po Hsien Chen ,  Ping-Chia Shih ,  Che Hao Kuo ,  Chia-Min Hung ,  Ching-Hua Yeh ,  Wan-Chun Liao

IPC: H01L23/00 ,  H04L9/32 ,  H01L29/06

CPC classification number: H01L23/57 ,  H04L9/3278 ,  H01L29/0649

Abstract: A physical unclonable function (PUF) generator including a substrate and semiconductor units is provided. Each of the semiconductor units includes an isolation structure, a first conductive line, and a second conductive line. The isolation structure is located in the substrate. The isolation structure has a first protrusion portion and a recess. The first protrusion portion and the recess are adjacent to each other. The first conductive line is located above the first protrusion portion and the recess. The second conductive line is located above the first conductive line. At least one short circuit randomly exists between at least one of the first conductive lines and at least one of the second conductive lines in at least one of the semiconductor units.

公开(公告)号：US20220293615A1

公开(公告)日：2022-09-15

申请号：US17198268

申请日：2021-03-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Min Hung ,  Ping-Chia Shih ,  Che-Hao Kuo ,  Kuei-Ya Chuang ,  Ssu-Yin Liu ,  Po-Hsien Chen ,  Wan-Chun Liao

IPC: H01L27/11521 ,  H01L29/423 ,  H01L29/788 ,  H01L21/28 ,  H01L29/66

Abstract: A method of forming a flash memory cell includes the following steps. A first dielectric layer and a floating gate layer are deposited on a substrate sequentially. Three blocking structures having oblique sidewalls broaden from bottom to top penetrating through the first dielectric layer and the floating gate layer are formed. A first part and a second part of the floating gate layer between two adjacent blocking structures are etched respectively, so that a first floating gate having two sharp top corners and oblique sidewalls, and a second floating gate having two sharp top corners and oblique sidewalls, are formed. The three blocking structures are removed. A first isolating layer and a first selective gate covering the first floating gate are formed and a second isolating layer and a second selective gate covering the second floating gate are formed. A flash memory cell formed by said method is also provided.

公开(公告)号：US10020393B2

公开(公告)日：2018-07-10

申请号：US14886108

申请日：2015-10-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Yin Hsiao ,  Chia-Min Hung

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/06 ,  H01L29/417 ,  H01L29/66 ,  H01L21/4763 ,  H01L21/471 ,  H01L21/4757 ,  H01L21/441

CPC classification number: H01L29/7823 ,  H01L21/441 ,  H01L21/471 ,  H01L21/47573 ,  H01L21/4763 ,  H01L21/47635 ,  H01L29/0611 ,  H01L29/0653 ,  H01L29/24 ,  H01L29/404 ,  H01L29/407 ,  H01L29/41725 ,  H01L29/66689 ,  H01L29/66969 ,  H01L29/7816

Abstract: The present invention provides a laterally diffused metal-oxide-semiconductor (LDMOS) transistor and a manufacturing method thereof. The LDMOS transistor includes a semiconductor substrate, an insulation structure, agate structure, and a plurality of floating electrodes. The insulation structure is disposed in the semiconductor substrate. The gate structure is disposed on the semiconductor substrate. The floating electrodes are embedded in the insulation structure, wherein the floating electrode closest to the gate structure protrudes from a top surface of the insulation structure or the gate structure includes at least one branch portion embedded in the insulation structure, and the floating electrodes are separated from the gate structure.