公开(公告)号：US20250022905A1

公开(公告)日：2025-01-16

申请号：US18900947

申请日：2024-09-30

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US20180197819A1

公开(公告)日：2018-07-12

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/768 ,  H01L21/02

CPC classification number: H01L23/53295 ,  H01L23/5283 ,  H01L23/53228

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.

公开(公告)号：US12176375B2

公开(公告)日：2024-12-24

申请号：US17322599

申请日：2021-05-17

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US11527605B2

公开(公告)日：2022-12-13

申请号：US17364935

申请日：2021-07-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shu-Ji Chen ,  Jing Feng ,  Xiao-Hong Jiang ,  Ching-Hwa Tey

IPC: H01L49/02 ,  H01L21/66 ,  H01L23/522 ,  H01L21/67 ,  G01R27/26 ,  G01R31/26

Abstract: A method for fabricating a MOMCAP includes steps as follows: An Nth metal layer is formed on a substrate according to an Nth expected capacitance value of the Nth metal layer. An Nth capacitance error value between an Nth actual capacitance value of the Nth metal layer and the Nth expected capacitance value is calculated. An N+1th expected capacitance value of an N+1th metal layer is adjusted to form an N+1th actual capacitance value according to the Nth capacitance error value, and the N+1th metal layer with an N+1th actual capacitance value is formed on the Nth metal layer according to the adjusted N+1th expected capacitance value, to make the sum of the Nth actual capacitance value and the N+1th actual capacitance value equal to the sum of the Nth expected capacitance value and the N+1th expected capacitance value. N is an integer greater than 1.

公开(公告)号：US20220336519A1

公开(公告)日：2022-10-20

申请号：US17322599

申请日：2021-05-17

Applicant: United Microelectronics Corp.

Inventor： Zhaoyao Zhan ,  Jing Feng ,  Qianwei Ding ,  Xiaohong Jiang ,  Ching-Hwa Tey

IPC: H01L27/146

Abstract: An image sensor structure including a substrate, a nanowire structure, a first conductive line, a second conductive line, and a third conductive line is provided. The nanowire structure includes a first doped layer, a second doped layer, a third doped layer, and a fourth doped layer sequentially stacked on the substrate. The first doped layer and the third doped layer have a first conductive type. The second doped layer and the fourth doped layer have a second conductive type. The first conductive line is connected to a sidewall of the second doped layer. The second conductive line is connected to a sidewall of the third doped layer. The third conductive line is connected to the fourth doped layer.

公开(公告)号：US10909299B1

公开(公告)日：2021-02-02

申请号：US16881020

申请日：2020-05-22

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wei Pang ,  Jing Feng ,  Xiaohong Jiang ,  Ching Hwa Tey

IPC: G06F17/50 ,  G03F1/36 ,  G06F30/392 ,  G06F119/06 ,  G06F30/373 ,  G06F30/337 ,  G06F30/347

Abstract: A method for stabilizing bandgap voltage includes the steps of: providing a first layout pattern designated with a first voltage; reducing a critical dimension of the first layout pattern for generating a second layout pattern corresponding to a second voltage; matching the second voltage with a target voltage; and then outputting the second layout pattern to a mask. Preferably, the first layout pattern and the second layout pattern include polysilicon resistor patterns.

公开(公告)号：US10332839B2

公开(公告)日：2019-06-25

申请号：US15400600

申请日：2017-01-06

Applicant: United Microelectronics Corp.

Inventor： Keen Zhang ,  Ji Feng ,  De-Jin Kong ,  Yun-Fei Li ,  Guo-Hai Zhang ,  Ching-Hwa Tey ,  Jing Feng

IPC: H01L21/00 ,  H01L23/532 ,  H01L21/768 ,  H01L23/528

Abstract: An interconnect structure including a substrate, at least one ultra-thick metal (UTM) layer, a first dielectric layer and at least one pad metal layer is provided. The at least one UTM layer is disposed on the substrate. The first dielectric layer is disposed on the at least one UTM layer and exposes the at least one UTM layer. A stress of the first dielectric layer is −150 Mpa to −500 Mpa. The at least one pad metal layer is disposed on the first dielectric layer and electrically connected to the at least one UTM layer exposed by the first dielectric layer.