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公开(公告)号：US11038014B2
公开(公告)日：2021-06-15
申请号：US16154704
申请日：2018-10-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US11244948B2
公开(公告)日：2022-02-08
申请号：US16158317
申请日：2018-10-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang
IPC: H01L27/108
Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.
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公开(公告)号：US20200083325A1
公开(公告)日：2020-03-12
申请号：US16154704
申请日：2018-10-08
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/06 , H01L21/027 , H01L29/66 , H01L21/033 , H01L21/311 , H01L21/3213
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US10700071B1
公开(公告)日：2020-06-30
申请号：US16258657
申请日：2019-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Gang-Yi Lin , Shih-Fang Tzou , Fu-Che Lee , Feng-Yi Chang , Ying-Chih Lin , Kai-Lou Huang , Yi-Ching Chang
IPC: H01L21/033 , H01L21/308 , H01L27/108
Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
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公开(公告)号：US20200083224A1
公开(公告)日：2020-03-12
申请号：US16158317
申请日：2018-10-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang
IPC: H01L27/108
Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, a first plug, a conductive pad and a capacitor structure. The first plug is disposed on the substrate, and the conductive pad is disposed on the first plug, with the conductive pad including a recessed shoulder portion at a top corner thereof. The capacitor structure is disposed on the conductive pad, to directly in connection with thereto.
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Patent Agency Ranking
公开(公告)号：US20200212048A1
公开(公告)日：2020-07-02
申请号：US16258657
申请日：2019-01-27
Applicant: UNITED MICROELECTRONICS CORP.
Inventor： Gang-Yi Lin , Shih-Fang Tzou , Fu-Che Lee , Feng-Yi Chang , Ying-Chih Lin , Kai-Lou Huang , Yi-Ching Chang
IPC: H01L27/108
Abstract: The present invention provides a method for forming a semiconductor pattern, comprising: firstly, a target layer is provided and a first material layer is formed on the target layer, and then a first pattern is formed on the first material layer, followed by a first self-aligned double pattering step is performed, a plurality of first grooves are formed in the first material layer. Next, a second material layer is formed on the first material layer, and a plurality of second grooves are formed in the second material layer. Next, transferring a pattern of the overlapping portion of the first grooves and the second grooves into the target layer, the target layer includes a plurality of third patterns and a plurality of fourth patterns, an area of each fourth pattern is larger than an area of each third pattern.
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公开(公告)号：US20200083317A1
公开(公告)日：2020-03-12
申请号：US16154680
申请日：2018-10-08
Inventor： Kai-Lou Huang , Fu-Che Lee , Feng-Yi Chang , Chieh-Te Chen , Meng-Chia Tsai
IPC: H01L49/02 , H01L23/532
Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.
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公开(公告)号：US11545547B2
公开(公告)日：2023-01-03
申请号：US17317912
申请日：2021-05-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/76 , H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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公开(公告)号：US11107879B2
公开(公告)日：2021-08-31
申请号：US16154680
申请日：2018-10-08
Inventor： Kai-Lou Huang , Fu-Che Lee , Feng-Yi Chang , Chieh-Te Chen , Meng-Chia Tsai
IPC: H01L27/108 , H01L49/02 , H01L23/532
Abstract: A capacitor structure includes a substrate having thereon a storage node contact, a cylinder-shaped bottom electrode disposed on the storage node contact, a supporting structure horizontally supporting a sidewall of the cylinder-shaped bottom electrode, a capacitor dielectric layer conformally covering the cylinder-shaped bottom electrode and the supporting structure, and a top electrode covering the capacitor dielectric layer. The supporting structure has a top surface that is higher than that of the cylinder-shaped bottom electrode. The top surface of the supporting structure has a V-shaped sectional profile.
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公开(公告)号：US20210265462A1
公开(公告)日：2021-08-26
申请号：US17317912
申请日：2021-05-12
Inventor： Feng-Yi Chang , Fu-Che Lee , Yi-Ching Chang , Kai-Lou Huang , Ying-Chih Lin , Gang-Yi Lin
IPC: H01L29/06 , H01L21/027 , H01L29/66 , H01L21/3213 , H01L21/033 , H01L21/311
Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a gate structure, a first dielectric layer, a second dielectric layer, a first plug and two metal lines. The substrate has a shallow trench isolation and an active area, and the gate structure is disposed on the substrate to cover a boundary between the active area and the shallow trench isolation. The first dielectric layer is disposed on the substrate, to cover the gate structure, and the first plug is disposed in the first dielectric layer to directly in contact with a conductive layer of the gate structure and the active area. The second dielectric layer is disposed on the first dielectric layer, with the first plug and the gate being entirely covered by the first dielectric layer and the second dielectric layer. The two metal lines are disposed in the second dielectric layer.
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