公开(公告)号：US20180198457A1

公开(公告)日：2018-07-12

申请号：US15460219

申请日：2017-03-15

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Hua FAN ,  Hadi HEIDARI ,  Franco MALOBERTI ,  Dagang LI ,  Daqian HU ,  Yuanjun CEN

IPC: H03M1/00 ,  H03M1/10 ,  H03M1/38

CPC classification number: H03M1/004 ,  H03M1/1009 ,  H03M1/38

Abstract: A method for improving a spurious free dynamic range and a signal-to-noise-and-distortion ratio of a capacitor-resistor combined successive approximation register analog-to-digital converter by capacitor re-configuration, the method including: 1) arranging 128 unit capacitors in a positive array and a negative array, respectively, dividing unit capacitors of symmetrical positions of the positive array and the negative array into groups to yield a total of 128 groups of capacitors; 2) acquiring 128 digital codes corresponding to 128 groups of capacitors; 3) sorting the 128 groups of capacitors from maximum to minimum according to the 128 digital codes obtained in 2), and recording the 128 groups of capacitors after sorting as C1-C128; and 4) selecting 64 groups of capacitors from C33 to C96, and reconfiguring the 64 groups of capacitors in capacitor arrays of the capacitor-resistor analog-to-digital converter.

公开(公告)号：US20210058091A1

公开(公告)日：2021-02-25

申请号：US16703828

申请日：2019-12-04

Applicant: University of Electronic Science and Technology of China

Inventor： Hua FAN ,  Chen WANG ,  Peng LEI ,  Dainan ZHANG ,  Quanyuan FENG ,  Lang FENG ,  Xiaopeng DIAO ,  Dagang LI ,  Kelin ZHANG ,  Daqian HU ,  Yuanjun CEN

IPC: H03M1/10 ,  H03M1/46

Abstract: A method of calibrating capacitive array of a resistor-capacitor hybrid successive approximation register analog-to-digital converter (RC-hybrid SAR ADC) that includes a high M-bit capacitor DAC and a low N-bit resistor DAC. The method includes: disposing n unit capacitors in each capacitive array of the RC-hybrid SAR ADC, wherein n=2M−1; sorting the capacitors in an ascending order according to their capacitances to form a sorted array, and selecting two capacitors Cu(n/2)*, Cu(n/2+1)* in the middle positions as a least significant bit (LSB) capacitor and a dummy capacitor, respectively; 4) obtaining a new array by forming each capacitor through adding two capacitors which have symmetrical positions with respect to the middle position(s) in the sorted array; and sorting the new array in an ascending order, and selecting the capacitor in the middle position as a higher bit capacitor. The method improves the static and dynamic performance of the SAR. ADC

公开(公告)号：US20190131998A1

公开(公告)日：2019-05-02

申请号：US16114300

申请日：2018-08-28

Applicant: UNIVERSITY OF ELECTRONIC SCIENCE AND TECHNOLOGY OF CHINA

Inventor： Hua FAN ,  Jingxuan YANG ,  Quanyuan FENG ,  Dagang LI ,  Daqian HU ,  Yuanjun CEN ,  Hadi HEIDARI ,  Franco MALOBERTI ,  Jingtao LI ,  Huaying SU

IPC: H03M1/46

Abstract: A method of arranging a capacitor array of a successive approximation register analog-to-digital converter in a successive approximation process, the method including: splitting a binary capacitor array into unit capacitors, then sorting, grouping, and rotating the original binary capacitive array involved in successive approximation conversion.