公开(公告)号：US20250079293A1

公开(公告)日：2025-03-06

申请号：US18379670

申请日：2023-10-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tai-Cheng Hou ,  Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/522 ,  H01L21/768

Abstract: A semiconductor device and a method of fabricating the same, includes at least one dielectric layer, a conductive structure, and a first insulator. The at least one dielectric layer includes a stacked structure having a low-k dielectric layer, an etching stop layer, and a conductive layer between the low-k dielectric layer and the etching stop layer. The conductive structure is disposed in the first dielectric layer. The first insulator is disposed between the conductive layer and the conductive structure.

公开(公告)号：US12207475B2

公开(公告)日：2025-01-21

申请号：US18209482

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US12127414B2

公开(公告)日：2024-10-22

申请号：US18209469

申请日：2023-06-13

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Yi-An Shih ,  Bin-Siang Tsai ,  Fu-Yu Tsai

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: A method for fabricating a semiconductor device includes the steps of first forming a magnetic tunneling junction (MTJ) on a substrate, forming a top electrode on the MTJ, forming an inter-metal dielectric (IMD) layer around the top electrode and the MTJ, forming a landing layer on the IMD layer and the MTJ, and then patterning the landing layer to form a landing pad. Preferably, the landing pad is disposed on the top electrode and the IMD layer adjacent to one side of the top electrode.

公开(公告)号：US20240290731A1

公开(公告)日：2024-08-29

申请号：US18660179

申请日：2024-05-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Chin-Chia Yang ,  Tai-Cheng Hou ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H01L23/00 ,  H01L21/02 ,  H01L23/522 ,  H01L29/417

CPC classification number: H01L23/562 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02348 ,  H01L23/5226 ,  H01L29/41725

Abstract: A warpage-reducing semiconductor structure includes a wafer. The wafer includes a front side and a back side. Numerous semiconductor elements are disposed at the front side. A silicon oxide layer is disposed at the back side. A UV-transparent silicon nitride layer covers and contacts the silicon oxide layer. The refractive index of the UV-transparent silicon nitride layer is between 1.55 and 2.10.

公开(公告)号：US12069960B2

公开(公告)日：2024-08-20

申请号：US17376179

申请日：2021-07-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Ching-Hua Hsu ,  Fu-Yu Tsai ,  Bin-Siang Tsai

IPC: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

CPC classification number: H10N50/10 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: The invention provides a semiconductor structure, the semiconductor structure includes a dielectric layer, a plurality of MTJ stacked elements and at least one dummy MTJ stacked element located in the dielectric layer, a first nitride layer covering at least the sidewalls of the MTJ stacked elements and the dummy MTJ stacked elements, a second nitride layer covering the top surfaces of the dummy MTJ stacked elements, the thickness of the second nitride layer is greater than the thickness of the first nitride layer, and a plurality of contact structures located in the dielectric layer and electrically connected with each MTJ stacked element.

公开(公告)号：US20230378313A1

公开(公告)日：2023-11-23

申请号：US17838258

申请日：2022-06-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Fu-Yu Tsai ,  Bin-Siang Tsai ,  Chung-Yi Chiu

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/778

CPC classification number: H01L29/66462 ,  H01L29/42316 ,  H01L29/778

Abstract: A manufacturing method of a semiconductor device includes the following steps. A gate structure is formed on a III-V compound semiconductor layer. A gate silicide layer and a source/drain silicide layer are formed by an anneal process. The gate silicide layer is formed on the gate structure, the source/drain silicide layer is formed on the III-V compound semiconductor layer, and a material composition of the gate silicide layer is different from a material composition of the source/drain silicide layer.

公开(公告)号：US11810818B2

公开(公告)日：2023-11-07

申请号：US17195648

申请日：2021-03-09

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Bin-Siang Tsai

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532

CPC classification number: H01L21/76858 ,  H01L21/7684 ,  H01L21/76802 ,  H01L21/76846 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238

Abstract: A method for fabricating semiconductor device includes the steps of: forming a dielectric layer on a substrate; forming a trench in the dielectric layer; forming a first liner in the trench, wherein the first liner comprises Co—Ru alloy; forming a metal layer on the first liner; and planarizing the metal layer and the first liner to form a metal interconnection.

公开(公告)号：US11688790B2

公开(公告)日：2023-06-27

申请号：US17143135

申请日：2021-01-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chih-Wei Chang ,  Yao-Hsien Chung ,  Shih-Wei Su ,  Hao-Hsuan Chang ,  Da-Jun Lin ,  Ting-An Chien ,  Bin-Siang Tsai

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20 ,  H01L29/423

CPC classification number: H01L29/66462 ,  H01L29/2003 ,  H01L29/4236 ,  H01L29/42364 ,  H01L29/7786

Abstract: An HEMT includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer. The composition of the first III-V compound layer is different from the composition of the second III-V compound layer. A trench is disposed within the first III-V compound layer and the second III-V compound layer. The trench has a first corner and a second corner. The first corner and the second corner are disposed in the first III-V compound layer. A first dielectric layer contacts a sidewall of the first corner. A second dielectric layer contacts a sidewall of the second corner. The first dielectric layer and the second dielectric layer are outside of the trench. A gate is disposed in the trench. A source electrode and a drain electrode are respectively disposed at two sides of the gate. A gate electrode is disposed directly on the gate.

公开(公告)号：US20230017965A1

公开(公告)日：2023-01-19

申请号：US17956772

申请日：2022-09-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Da-Jun Lin ,  Shih-Wei Su ,  Bin-Siang Tsai ,  Ting-An Chien

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/10 ,  H01L27/22

Abstract: A magnetic tunnel junction (MTJ) device includes a bottom electrode, a reference layer, a tunnel barrier layer, a free layer and a top electrode. The bottom electrode and the top electrode are facing each other. The reference layer, the tunnel barrier layer and the free layer are stacked from the bottom electrode to the top electrode, wherein the free layer includes a first ferromagnetic layer, a spacer and a second ferromagnetic layer, wherein the spacer is sandwiched by the first ferromagnetic layer and the second ferromagnetic layer, wherein the spacer includes oxidized spacer sidewall parts, the first ferromagnetic layer includes first oxidized sidewall parts, and the second ferromagnetic layer includes second oxidized sidewall parts. The present invention also provides a method of manufacturing a magnetic tunnel junction (MTJ) device.

公开(公告)号：US11189793B2

公开(公告)日：2021-11-30

申请号：US16589148

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Wei Su ,  Da-Jun Lin ,  Bin-Siang Tsai ,  Ya-Jyuan Hung ,  Ting-An Chien

IPC: H01L45/00 ,  H01L27/24

Abstract: A method of forming a resistive random access memory cell includes the following steps. A first electrode layer, a blanket resistive switching material layer and a second electrode layer are formed on a layer sequentially. The second electrode layer is patterned to form a second electrode. The blanket resistive switching material layer is patterned to form a resistive switching material layer. An oxygen implanting process is performed to implant oxygen in two sidewall parts of the resistive switching material layer.