公开(公告)号：US20240395930A1

公开(公告)日：2024-11-28

申请号：US18382561

申请日：2023-10-23

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Yue GAO ,  Jiawei WANG ,  Dingxiang MA ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/423

Abstract: A lateral power semiconductor device is provided and includes a second doping type substrate, a first doping type buried layer, a second doping type epitaxial layer, a first doping type drift area, a second doping type first body area, a first doping type drain area, a first doping type source area, a second doping type second body area, a dielectric layer, a control gate, a body electrode, second doping type polysilicon and first doping type polysilicon. The control gate is led out and connected to different potentials; when the device is in an off state, the control gate is connected to a low potential to assist the drift area in depletion; and when the device is in an on state, the control gate is connected to a high potential, and more carriers are induced on a silicon surface below the control gate.

公开(公告)号：US20250107137A1

公开(公告)日：2025-03-27

申请号：US18398222

申请日：2023-12-28

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Jiawei WANG ,  Dingxiang MA ,  Yue GAO ,  Gen LIU ,  Shengduo WANG ,  Yuanqing YE ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417

Abstract: A lateral power semiconductor device layout and a device structure belong to the technical field of power semiconductor devices. A method for designing a lateral power semiconductor device layout with high integrity and high cell density has the following advantages of reducing a specific on-resistance of the device, increasing a width of a channel per unit area, improving the current capability of the device, optimizing the static characteristic of the device, reducing the area of a drain region and the parasitic capacitance of the device, reducing the delay time of a cell switch caused by an excessively long gate electrode of a traditional finger cell, optimizing the dynamic characteristic of the device, optimizing the cell edge of the device and the curvature effect of a terminal, and reducing the pre-breakdown risk of the device.