公开(公告)号：US20230170411A1

公开(公告)日：2023-06-01

申请号：US17714176

申请日：2022-04-06

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Yong CHEN ,  Wenliang LIU ,  Dong FANG ,  Fabei ZHANG ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L29/40 ,  H01L21/265 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66

CPC classification number: H01L29/7813 ,  H01L29/063 ,  H01L29/1095 ,  H01L29/407 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/761 ,  H01L29/66734

Abstract: A bidirectional conduction trench gate power MOS device and a manufacturing method thereof are provided. A gate electrode, a source electrode and a drain electrode are formed on a surface of a silicon wafer to realize a bidirectional conduction and bidirectional blocking power MOS device used in an application environment such as lithium battery BMS protection. A device structure of the bidirectional conduction trench gate power MOS device has advantages compared with double-transistor series connection used in a conventional BMS and other structures for realizing a bidirectional conduction: firstly, the bidirectional conduction trench gate power MOS device needs to occupy half or less area compared with a conventional mode, improving a degree of integration; secondly, the device structure has a simple manufacturing process and a low manufacturing cost reducing manufacturing problems; thirdly, the drain electrode and the source electrode of the device structure are exchanged to realize a symmetrical structure.

公开(公告)号：US20220367712A1

公开(公告)日：2022-11-17

申请号：US17367442

申请日：2021-07-05

Applicant: University of Electronic Science and Technology of China

Inventor： Ming QIAO ,  Liu YUAN ,  Zhao WANG ,  Wenliang LIU ,  Bo ZHANG

IPC: H01L29/78 ,  H01L29/40 ,  H01L29/06 ,  H01L29/10

Abstract: A power semiconductor device includes a P-type substrate, an N-type well region, a P-type body region, a gate oxide layer, a polysilicon gate, a first oxide layer, a first N+ contact region, a first P+ contact region, drain metal, a first-type doped region, and a gate oxide layer. An end of the P-type body region is flush with or exceeds an end of the polysilicon gate, wherein Cgd of the power semiconductor device is reduced and a switching frequency of the power semiconductor device is increased. A polysilicon field plate connected with a source is introduced over a drift region that is not only shield an influence of the polysilicon gate on the drift region, thereby eliminating Cgd caused by overlapping of traditional polysilicon gate and drift region, but also enable the power semiconductor device to have strong robustness against an hot carrier effect.