公开(公告)号：US07412369B1

公开(公告)日：2008-08-12

申请号：US09591621

申请日：2000-06-09

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: G06F17/50

CPC classification number: G06F11/3457

Abstract: There is disclosed an apparatus for designing and optimizing a memory for use in an embedded processing system. The apparatus comprises: 1) a simulation controller for simulating execution of a test program to be executed by the embedded processing system; 2) a memory access monitor for monitoring memory accesses to a simulated memory space during the simulated execution of the test program, wherein the memory access monitor generates memory usage statistical data associated with the monitored memory accesses; and 3) a memory optimization controller for comparing the memory usage statistical data and one or more predetermined design criteria associated with the embedded processing system and, in response to the comparison, determining at least one memory configuration capable of satisfying the one or more predetermined design criteria.

Abstract translation: 公开了一种用于设计和优化用于嵌入式处理系统的存储器的装置。 该装置包括：1）模拟控制器，用于模拟由嵌入式处理系统执行的测试程序的执行; 2）一种存储器访问监视器，用于在所述测试程序的模拟执行期间监视对模拟存储器空间的存储器访问，其中所述存储器访问监视器生成与所监视的存储器访问相关联的存储器使用统计数据; 以及3）存储器优化控制器，用于比较存储器使用统计数据和与嵌入式处理系统相关联的一个或多个预定设计标准，并且响应于该比较，确定能够满足一个或多个预定设计的至少一个存储器配置 标准

公开(公告)号：US08164159B1

公开(公告)日：2012-04-24

申请号：US12838158

申请日：2010-07-16

Applicant: William Eddie Armstrong ,  Michael Shannon McCorquodale ,  Vidyabhusan Gupta ,  Justin O'Day ,  Nader Fayyaz ,  Gordon Carichner

Inventor： William Eddie Armstrong ,  Michael Shannon McCorquodale ,  Vidyabhusan Gupta ,  Justin O'Day ,  Nader Fayyaz ,  Gordon Carichner

IPC: H01L29/86

CPC classification number: H03B5/1228 ,  H01L29/0619 ,  H01L29/86 ,  H01L2224/48463 ,  H01L2224/73265 ,  H03B5/1215 ,  H03B5/1234 ,  H03B5/124

Abstract: A reference signal generator includes an integrated circuit substrate having a semiconductor resonator therein. The resonator includes an inductor extending adjacent a first surface of the integrated circuit substrate. A vertically-stacked composite of at least first and second electrically insulating dielectric layers is provided on the integrated circuit substrate. The vertically-stacked composite covers a portion of the first surface, which extends opposite the inductor. A first electrically conductive shielding layer is provided on a portion of the second electrically insulating dielectric layer extending opposite the inductor. The first electrically conductive shielding layer may encapsulate exposed portions of the first and second electrically insulating dielectric layers. The shielding layer may operate as an electromagnetic shield between the inductor and an external structure, such as an integrated circuit package, and also shield against environmental contamination (e.g., external moisture penetration).

Abstract translation: 参考信号发生器包括其中具有半导体谐振器的集成电路基板。 谐振器包括在集成电路基板的第一表面附近延伸的电感器。 在集成电路基板上设置有至少第一和第二电绝缘介电层的垂直堆叠的复合材料。 垂直堆叠的复合物覆盖与电感器相对延伸的第一表面的一部分。 在与电感器相对延伸的第二电绝缘介电层的一部分上设置有第一导电屏蔽层。 第一导电屏蔽层可以封装第一和第二电绝缘介电层的暴露部分。 屏蔽层可以作为电感器和诸如集成电路封装的外部结构之间的电磁屏蔽来操作，并且还可以防止环境污染（例如，外部湿气穿透）。

公开(公告)号：US20100271144A1

公开(公告)日：2010-10-28

申请号：US12766205

申请日：2010-04-23

Applicant: Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Vidyabhusan Gupta ,  Nathaniel Charles Gaskin ,  Nader Fayyaz

Inventor： Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Vidyabhusan Gupta ,  Nathaniel Charles Gaskin ,  Nader Fayyaz

IPC: H03B5/12

CPC classification number: H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1271 ,  H03B5/1293

Abstract: Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal having a resonant frequency, with the reference resonator having a first temperature dependence; and a plurality of switchable circuits, with at least one switchable circuit providing a second temperature dependence opposing the first temperature dependence to maintain the resonant frequency within a predetermined variance over a temperature variation. A wide variety of switchable circuits are disclosed, including a transistor having an on resistance value greater than a nominal resistance, a resistor coupled to a transistor or other switch, and circuit comprising a first reactance coupled to a first switch, with a second reactance coupled to a resistance and a second switch coupled in series to the second reactance or to the resistance. Various coatings may also be applied to an integrated circuit embodiment, such as a silicone coating on a first surface and a metal layer on a second surface.

Abstract translation: 示例性实施例提供了参考信号发生器，其具有在指定范围内的温度变化的预定方差内的参考或中心频率。 示例性装置包括参考谐振器，以产生具有谐振频率的第一参考信号，参考谐振器具有第一温度依赖性; 以及多个可切换电路，其中至少一个可切换电路提供与第一温度依赖性相反的第二温度依赖性，以将谐振频率保持在温度变化以上的预定变化范围内。 公开了各种各样的可切换电路，包括具有大于标称电阻的导通电阻值的晶体管，耦合到晶体管或其它开关的电阻器，以及包括耦合到第一开关的第一电抗的电路，第二电抗耦合 耦合到与第二电抗或电阻串联耦合的电阻和第二开关。 各种涂层也可以应用于集成电路实施例，例如第一表面上的硅氧烷涂层和第二表面上的金属层。

公开(公告)号：US06469538B1

公开(公告)日：2002-10-22

申请号：US09590499

申请日：2000-06-09

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: G01R3126

CPC classification number: G01R31/3004

Abstract: An apparatus for monitoring a load current drawn by an electrical circuit in a wire includes: 1) a Lorentz force MOS transistor having a first drain current (ID1) and a second drain current (ID2), wherein the Lorentz force MOS transistor is disposed proximate the wire carrying the load current and wherein a magnetic force generated by the load current increases a first current difference between the first drain current and a second drain current; 2) a current difference amplification circuit for detecting the first current difference between the first drain current and the second drain current and generating an amplified output signal; and 3) a current monitoring circuit coupled to the current difference amplification circuit capable of detecting and measuring the amplified output signal.

Abstract translation: 一种用于监测由电线中的电线牵引的负载电流的装置，包括：1）具有第一漏极电流（ID1）和第二漏极电流（ID2）的洛伦兹力MOS晶体管，其中所述洛伦兹力MOS晶体管靠近 承载负载电流的线，其中由所述负载电流产生的磁力增加所述第一漏极电流和第二漏极电流之间的第一电流差; 2）电流差放大电路，用于检测第一漏极电流和第二漏极电流之间的第一电流差并产生放大的输出信号; 以及3）耦合到能够检测和测量放大的输出信号的电流差分放大电路的电流监视电路。

公开(公告)号：US06839888B2

公开(公告)日：2005-01-04

申请号：US10407100

申请日：2003-04-03

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: G06F15/78 ,  H03K19/00

CPC classification number: G06F15/7867

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1) a plurality of configurable logic blocks, including a first CLB having an N-bit output and a second CLB having an N-bit input; 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches, wherein the interconnect switch controller in a first switch configuration causes a firsts group of interconnects coupled to the N-bit output of the first CLB to be coupled to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping and wherein the interconnect switch controller in a second switch configuration causes the first group of interconnects to be coupled to the second group of interconnects according to a second connection mapping.

Abstract translation: 公开了一种现场可编程门阵列（FPGA），其在互连中而不是FPGA的可配置逻辑块中执行位交换功能。 FPGA包括：1）多个可配置逻辑块，包括具有N位输出的第一CLB和具有N位输入的第二CLB; 2）多个互连; 3）多个互连开关，用于将所述多个互连中的一个互连到所述多个可配置逻辑块的输入和输出; 以及4）用于控制所述多个互连开关的互连开关控制器，其中所述第一开关配置中的所述互连开关控制器使得耦合到所述第一CLB的N位输出的第一组互连耦合到第二组 互连，其根据第一连接映射耦合到第二CLB的N位输入，并且其中第二交换机配置中的互连开关控制器根据第二连接映射使第一组互连耦合到第二组互连 。

公开(公告)号：US06681354B2

公开(公告)日：2004-01-20

申请号：US09773104

申请日：2001-01-31

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: G01R313177

CPC classification number: G01R31/318519

Abstract: There is disclosed a field programmable gate array for use in an integrated processing system capable of testing other embedded circuit components in the integrated processing system. The field programmable gate array detects a trigger signal (such as a power reset) in the integrated processing system. In response to the trigger signal, the field programmable gate array receives first test program instructions from a first external source and executes the first test program instructions in order to test the other embedded circuit components in the integrated processing system. When testing of the other embedded circuit components is complete, the field programmable gate array loads its normal operating code and performs its normal functions.

Abstract translation: 公开了一种用于能够测试集成处理系统中的其它嵌入式电路部件的集成处理系统中的现场可编程门阵列。 现场可编程门阵列检测集成处理系统中的触发信号（例如功率复位）。 响应于触发信号，现场可编程门阵列从第一外部源接收第一测试程序指令，并执行第一测试程序指令，以便测试集成处理系统中的其他嵌入式电路组件。 当其他嵌入式电路组件的测试完成时，现场可编程门阵列加载其正常的操作码并执行其正常功能。

公开(公告)号：US06577158B2

公开(公告)日：2003-06-10

申请号：US09774891

申请日：2001-01-31

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: H03K19177

CPC classification number: G06F15/7867

Abstract: There is disclosed a field programmable gate array (FPGA) that performs bit swapping functions in the interconnects rather than in the configurable logic blocks of the FPGA. The FPGA comprises: 1) a plurality of configurable logic blocks, including a first CLB having an N-bit output and a second CLB having an N-bit input; 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches, wherein the interconnect switch controller in a first switch configuration causes a first group of interconnects coupled to the N-bit output of the first CLB to be coupled to a second group of interconnects coupled to the N-bit input of the second CLB according to a first connection mapping and wherein the interconnect switch controller in a second switch configuration causes the first group of interconnects to be coupled to the second group of interconnects according to a second connection mapping.

公开(公告)号：US08134414B2

公开(公告)日：2012-03-13

申请号：US12766205

申请日：2010-04-23

Applicant: Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Vidyabhusan Gupta ,  Nathaniel Charles Gaskin ,  Nader Fayyaz

Inventor： Michael Shannon McCorquodale ,  Scott Michael Pernia ,  Vidyabhusan Gupta ,  Nathaniel Charles Gaskin ,  Nader Fayyaz

IPC: H03B5/12 ,  H03L1/00 ,  H03L5/00 ,  H03L7/099

CPC classification number: H03B5/04 ,  H03B5/1215 ,  H03B5/1228 ,  H03B5/1243 ,  H03B5/1271 ,  H03B5/1293

Abstract: Exemplary embodiments provide a reference signal generator having a reference or center frequency within a predetermined variance over variations in temperature within a specified range. An exemplary apparatus comprises a reference resonator to generate a first reference signal having a resonant frequency, with the reference resonator having a first temperature dependence; and a plurality of switchable circuits, with at least one switchable circuit providing a second temperature dependence opposing the first temperature dependence to maintain the resonant frequency within a predetermined variance over a temperature variation. A wide variety of switchable circuits are disclosed, including a transistor having an on resistance value greater than a nominal resistance, a resistor coupled to a transistor or other switch, and circuit comprising a first reactance coupled to a first switch, with a second reactance coupled to a resistance and a second switch coupled in series to the second reactance or to the resistance. Various coatings may also be applied to an integrated circuit embodiment, such as a silicone coating on a first surface and a metal layer on a second surface.

Abstract translation: 示例性实施例提供了参考信号发生器，其具有在指定范围内的温度变化的预定方差内的参考或中心频率。 示例性装置包括参考谐振器，以产生具有谐振频率的第一参考信号，参考谐振器具有第一温度依赖性; 以及多个可切换电路，其中至少一个可切换电路提供与第一温度依赖性相反的第二温度依赖性，以将谐振频率保持在温度变化以上的预定变化范围内。 公开了各种各样的可切换电路，包括具有大于标称电阻的导通电阻值的晶体管，耦合到晶体管或其它开关的电阻器，以及包括耦合到第一开关的第一电抗的电路，第二电抗耦合 耦合到与第二电抗或电阻串联耦合的电阻和第二开关。 各种涂层也可以应用于集成电路实施例，例如第一表面上的硅氧烷涂层和第二表面上的金属层。

公开(公告)号：US06813677B1

公开(公告)日：2004-11-02

申请号：US09586134

申请日：2000-06-02

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: G06F1200

CPC classification number: G11C8/00

Abstract: There is disclosed a memory capable of storing a present value and at least one past value of a variable accessible by a first memory address. The memory comprises a memory block comprising R rows of memory cells and a row address decoder for decoding the first memory address. During a read operation, the row address decoder causes data to be retrieved from a row in which data stored to the first memory address was last written. During a write operation, the row address decoder causes data to be stored in a next-sequential row following the last-written row.

Abstract translation: 公开了一种存储器，其能够存储可由第一存储器地址访问的变量的当前值和至少一个过去值。 该存储器包括一个包括R行存储单元的存储块和一个用于解码第一存储器地址的行地址解码器。 在读取操作期间，行地址解码器使得从最后写入存储到第一存储器地址的数据的行中检索数据。 在写入操作期间，行地址解码器使得数据被存储在最后写入行之后的后续行中。

公开(公告)号：US06483344B2

公开(公告)日：2002-11-19

申请号：US09773320

申请日：2001-01-31

Applicant: Vidyabhusan Gupta

Inventor： Vidyabhusan Gupta

IPC: H01L2500

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  H03K19/1778

Abstract: There is disclosed a field programmable gate array that performs in the interconnect matrix selected Boolean logic functions, such as OR gates and NOR gates, normally performed in the configurable logic blocks of the FPGA. The field programmable gate array comprises: 1) a plurality of configurable logic blocks (CLBs); 2) a plurality of interconnects; 3) a plurality of interconnect switches for coupling ones of the plurality of interconnects to each other and to inputs and outputs of the plurality of configurable logic blocks; and 4) an interconnect switch controller for controlling the plurality of interconnect switches. The interconnect switch controller in a first switch configuration causes a first interconnect to be coupled to an output of a first CLB, causes a second interconnect to be coupled to an output of a second CLB, causes the first and second interconnects to be coupled to a third interconnect, and causes the third interconnect to be coupled to a pull-up device coupled to a power supply source of the field programmable gate array. The first, second and third interconnects and the pull-up device thereby form a two-input OR gate.

Abstract translation: 公开了一种现场可编程门阵列，其在互连矩阵中执行通常在FPGA的可配置逻辑块中执行的所选择的布尔逻辑功能，例如OR门和NOR门。 现场可编程门阵列包括：1）多个可配置逻辑块（CLB）; 2）多个互连; 3）多个互连开关，用于将所述多个互连中的一个互连到所述多个可配置逻辑块的输入和输出; 以及4）用于控制所述多个互连开关的互连开关控制器。 在第一开关配置中的互连开关控制器使得第一互连件耦合到第一CLB的输出端，使第二互连件耦合到第二CLB的输出，使第一和第二互连件耦合到 第三互连，并且使第三互连耦合到耦合到现场可编程门阵列的电源的上拉器件。 因此，第一，第二和第三互连和上拉器件形成双输入或门。