Compiler-generated invocation stubs for data parallel programming model
    1.
    发明授权
    Compiler-generated invocation stubs for data parallel programming model 有权
    用于数据并行编程模型的编译器生成的调用存根

    公开(公告)号:US08589867B2

    公开(公告)日:2013-11-19

    申请号:US12819108

    申请日:2010-06-18

    IPC分类号: G06F9/44

    CPC分类号: G06F8/45

    摘要: Described herein are techniques for generating invocation stubs for a data parallel programming model so that a data parallel program written in a statically-compiled high-level programming language may be more declarative, reusable, and portable than traditional approaches. With some of the described techniques, invocation stubs are generated by a compiler and those stubs bridge a logical arrangement of data parallel computations to the actual physical arrangement of a target data parallel hardware for that data parallel computation.

    摘要翻译: 这里描述的是用于生成用于数据并行编程模型的调用存根的技术,使得以静态编译的高级编程语言编写的数据并行程序可以比传统方法更具声明性,可重复使用和便携式。 利用一些所描述的技术,调用存根由编译器生成,并且这些存根将数据并行计算的逻辑排列与用于该数据并行计算的目标数据并行硬件的实际物理排列相结合。

    Transforming addressing alignment during code generation
    2.
    发明授权
    Transforming addressing alignment during code generation 有权
    在代码生成期间转换寻址对齐

    公开(公告)号:US08539458B2

    公开(公告)日:2013-09-17

    申请号:US13158077

    申请日:2011-06-10

    CPC分类号: G06F8/44

    摘要: The present invention extends to methods, systems, and computer program products for changing addressing mode during code generation. Generally, embodiments of the invention use a compiler transformation to transform lower level code from one address alignment to another address alignment. The transformation can be based upon assumptions of a source programming language. Based on the assumptions, the transformation can eliminate arithmetic operations that compensate for different addressing alignment, resulting in more efficient code. Some particular embodiments use a compiler transformation to transform an Intermediate Representation (“IR”) from one-byte addressing alignment into multi-byte (e.g., four-byte) addressing alignment.

    摘要翻译: 本发明扩展到用于在代码生成期间改变寻址模式的方法,系统和计算机程序产品。 通常,本发明的实施例使用编译器转换来将较低级别的代码从一个地址对齐转换到另一个地址对齐。 转换可以基于源程序设计语言的假设。 基于这些假设,转换可以消除补偿不同寻址对齐的算术运算,从而产生更有效的代码。 一些特定实施例使用编译器变换将中间表示(“IR”)从一字节寻址对准转换为多字节(例如,四字节)寻址对齐。

    RECONSTRUCTING PROGRAM CONTROL FLOW
    3.
    发明申请
    RECONSTRUCTING PROGRAM CONTROL FLOW 有权
    重新编制程序控制流程

    公开(公告)号:US20120159458A1

    公开(公告)日:2012-06-21

    申请号:US12972198

    申请日:2010-12-17

    IPC分类号: G06F9/45

    CPC分类号: G06F8/51 G06F8/53

    摘要: The present invention extends to methods, systems, and computer program products for reconstructing program control flow. Embodiments include implementing or morphing a control flow graph (“CFG”) into an arbitrary loop structure to reconstruct (preserve) control flow from original source code. Loop structures can be optimized and can adhere to target platform constraints. In some embodiments, C++ source code (a first higher level format) is translated into a CFG (a lower level format). The CFG is then translated into HLSL source code (a second different higher level format) for subsequent compilation into SLSL bytecode (that can then be executed at a Graphical Processing Unit (“GPU”)). The control flow from the C++ source code is preserved in the HLSL source code.

    摘要翻译: 本发明扩展到用于重建程序控制流的方法,系统和计算机程序产品。 实施例包括将控制流程图(“CFG”)实现或变形为任意循环结构,以重构(保留)来自原始源代码的控制流程。 循环结构可以进行优化,并可以遵守目标平台约束。 在一些实施例中,将C ++源代码(第一较高级格式)转换成CFG(较低级格式)。 然后将CFG转换为HLSL源代码(第二种不同的较高级别格式),以便后续编译成SLSL字节码(然后可以在图形处理单元(“GPU”)中执行)。 来自C ++源代码的控制流将保留在HLSL源代码中。

    ACTION FRAMEWORK IN SOFTWARE TRANSACTIONAL MEMORY
    4.
    发明申请
    ACTION FRAMEWORK IN SOFTWARE TRANSACTIONAL MEMORY 有权
    软件交易记忆中的动作框架

    公开(公告)号:US20110314230A1

    公开(公告)日:2011-12-22

    申请号:US12819494

    申请日:2010-06-21

    IPC分类号: G06F12/00 G06F17/30

    CPC分类号: G06F9/467 G06F9/526

    摘要: A software transactional memory system implements a lightweight key-based action framework. The framework includes a set of unified application programming interfaces (APIs) exposed by an STM library that allow clients to implement actions that can be registered, queried, and updated using specific keys by transactions or transaction nests in STM code. Each action includes a key, state information, and a set of one or more callbacks that can be hooked to the validation, commit, abort, and/or re-execution phases of transaction execution. The actions extend the built-in concurrency controls of the STM system with customized control logics, support transaction nesting semantics, and enable integration with garbage collection systems.

    摘要翻译: 软件事务内存系统实现了一个轻量级的基于键盘的动作框架。 该框架包括由STM库公开的一组统一的应用程序编程接口(API),允许客户端通过STM代码中的事务处理或事务处理实现使用特定密钥进行注册,查询和更新的操作。 每个动作包括一个密钥,状态信息和一组可以挂接到事务执行的验证,提交,中止和/或重新执行阶段的回调。 该操作通过定制的控制逻辑扩展了STM系统的内置并发控制,支持事务嵌套语义,并实现了与垃圾收集系统的集成。

    ARRAY OBJECT CONCURRENCY IN STM
    5.
    发明申请
    ARRAY OBJECT CONCURRENCY IN STM 有权
    阵列对象在STM中的约束

    公开(公告)号:US20100083257A1

    公开(公告)日:2010-04-01

    申请号:US12243371

    申请日:2008-10-01

    IPC分类号: G06F9/46 G06F12/16

    摘要: A software transactional memory system is provided that creates an array of transactional locks for each array object that is accessed by transactions. The system divides the array object into non-overlapping portions and associates each portion with a different transactional lock. The system acquires transactional locks for transactions that access corresponding portions of the array object. By doing so, different portions of the array object can be accessed by different transactions concurrently. The system may use a shared shadow or undo copy for accesses to the array object.

    摘要翻译: 提供了一种软件事务性内存系统,为每个由事务访问的数组对象创建一个事务锁数组。 该系统将数组对象划分为非重叠部分,并将每个部分与不同的事务锁相关联。 系统为访问数组对象的相应部分的事务获取事务锁。 通过这样做,可以通过不同的事务同时访问数组对象的不同部分。 系统可以使用共享的阴影或复制副本来访问数组对象。

    Aliasing buffers
    6.
    发明授权
    Aliasing buffers 有权
    混叠缓冲区

    公开(公告)号:US08990515B2

    公开(公告)日:2015-03-24

    申请号:US13160373

    申请日:2011-06-14

    IPC分类号: G06F9/45 G06F9/445

    CPC分类号: G06F8/51 G06F9/44536

    摘要: The present invention extends to methods, systems, and computer program products for aliasing buffers. Embodiment of the inventions supporting buffer aliasing through introduction of a level of indirection between a source program's buffer accesses and the target executable physical buffers, and binding the logical buffer accesses to actual physical buffer accesses at runtime. A variety of techniques for can be used supporting runtime aliasing of buffers, in a system which otherwise disallows such runtime aliasing between separately defined buffers in the target executable code. Binding of logical buffer accesses in the source program to the actual physical buffers defined in the target executable code is delayed until runtime.

    摘要翻译: 本发明扩展到用于混叠缓冲器的方法,系统和计算机程序产品。 本发明的实施例通过引入源程序的缓冲器访问和目标可执行物理缓冲器之间的间接级别来支持缓冲器混叠,并且在运行时将逻辑缓冲器访问绑定到实际物理缓冲器访问。 可以使用各种技术来支持缓冲器的运行时混叠,在系统中,否则不允许在目标可执行代码中的单独定义的缓冲区之间的这种运行时混叠。 将源程序中的逻辑缓冲区访问绑定到目标可执行代码中定义的实际物理缓冲区将被延迟到运行时。

    Debugging in a multiple address space environment
    7.
    发明授权
    Debugging in a multiple address space environment 有权
    在多地址空间环境中进行调试

    公开(公告)号:US08677322B2

    公开(公告)日:2014-03-18

    申请号:US13172521

    申请日:2011-06-29

    IPC分类号: G06F9/44

    CPC分类号: G06F8/41 G06F11/3624

    摘要: The present invention extends to methods, systems, and computer program products for debugging in a multiple address space environment. Embodiments of the invention include techniques for recording debug information used for translating between an abstract unified address space and multiple address spaces at a target system (e.g., a co-processor, such as, a GPU or other accelerator). A table is stored in the recorded debug information. The table includes one or more entries mapping compiler assigned IDs to address spaces. During debugging within a symbolic debugger, the recorded debug information can be used for viewing program data across multiple address spaces in a live debugging session.

    摘要翻译: 本发明扩展到用于在多地址空间环境中进行调试的方法,系统和计算机程序产品。 本发明的实施例包括用于记录用于在抽象统一地址空间和目标系统(例如协同处理器,例如GPU或其他加速器)处的多个地址空间之间进行翻译的调试信息的技术。 表中存储有记录的调试信息。 该表包括将编译器分配的ID映射到地址空间的一个或多个条目。 在符号调试器调试期间,记录的调试信息可用于在实时调试会话中跨多个地址空间查看程序数据。

    EMULATING POINTERS
    8.
    发明申请
    EMULATING POINTERS 有权
    模拟点

    公开(公告)号:US20120167062A1

    公开(公告)日:2012-06-28

    申请号:US12979094

    申请日:2010-12-27

    IPC分类号: G06F9/45

    CPC分类号: G06F9/455 G06F8/434

    摘要: The present invention extends to methods, systems, and computer program products for emulating pointers. Pointers can be emulated by replacing the pointers with a pair and replacing each dereference site with a switch on the tag and a switch body that executes the emulated pointer access on the corresponding variable the pointer points to. Data flow optimizations can be used to reduce the number of switches and/or reduce the number of cases which need be considered at each emulated pointer access sites.

    摘要翻译: 本发明扩展到用于模拟指针的方法,系统和计算机程序产品。 可以通过用对替换指针来替换指针,并使用标签上的开关替换每个解引用站点,以及在指针指向的相应变量上执行仿真指针访问的交换机主体。 可以使用数据流优化来减少交换机的数量和/或减少在每个仿真指针访问站点需要考虑的情况的数量。

    READ-ONLY COMMUNICATION OPERATOR
    9.
    发明申请
    READ-ONLY COMMUNICATION OPERATOR 有权
    只读通信操作器

    公开(公告)号:US20120131552A1

    公开(公告)日:2012-05-24

    申请号:US12949908

    申请日:2010-11-19

    IPC分类号: G06F9/45 G06F9/44

    CPC分类号: G06F8/314 G06F8/458

    摘要: A high level programming language provides a read-only communication operator that prevents a computational space from being written. An indexable type with a rank and element type defines the computational space. For an input indexable type, the read-only communication operator produces an output indexable type with the same rank and element type as the input indexable type but ensures that the output indexable type may not be written. The read-only communication operator ensures that any attempt to write to the output indexable type will be detected as an error at compile time.

    摘要翻译: 高级编程语言提供了一种只读通信操作符,防止写入计算空间。 具有等级和元素类型的可索引类型定义了计算空间。 对于输入可索引类型,只读通信运算符产生具有与输入可索引类型相同的排名和元素类型的输出可索引类型,但确保可能不写入输出可索引类型。 只读通信运算符确保在编译时检测到对输出可索引类型的任何尝试都将作为错误检测。

    STM WITH GLOBAL VERSION OVERFLOW HANDLING
    10.
    发明申请
    STM WITH GLOBAL VERSION OVERFLOW HANDLING 有权
    STM与全球版本的超流量处理

    公开(公告)号:US20100211931A1

    公开(公告)日:2010-08-19

    申请号:US12370742

    申请日:2009-02-13

    IPC分类号: G06F9/44

    CPC分类号: G06F9/466 G06F11/141

    摘要: A software transactional memory system is provided with overflow handling. The system includes a global version counter with an epoch number and a version number. The system accesses the global version counter prior to and subsequent to memory accesses of transactions to validate read accesses of the transaction. The system includes mechanisms to detect global version number overflow and may allow some or all transactions to execute to completion subsequent to the global version number overflowing. The system also provides publication, privatization, and granular safety properties.

    摘要翻译: 软件事务内存系统提供溢出处理。 该系统包括具有时代号和版本号的全局版本计数器。 系统在事务的内存访问之前和之后访问全局版本计数器,以验证事务的读取访问。 该系统包括检测全局版本号溢出的机制,并且可允许一些或所有事务在全球版本号码溢出之后执行完成。 该系统还提供出版物,私有化和粒状安全属性。