公开(公告)号：US20240428848A1

公开(公告)日：2024-12-26

申请号：US18213647

申请日：2023-06-23

Applicant: XILINX, INC.

Inventor： Nui CHONG ,  Jing Jing CHEN ,  Babruwahan Tulshiram GADE ,  Shidong ZHOU

IPC: G11C11/4093 ,  G11C11/4099

Abstract: A memory device includes a first bit cell comprising a first inverter, the first inverter comprising a p-type transistor coupled to an n-type transistor, and header circuitry coupled to the first inverter and comprising a first header transistor and a second header transistor, the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage.

公开(公告)号：US20210133107A1

公开(公告)日：2021-05-06

申请号：US16670570

申请日：2019-10-31

Applicant: XILINX, INC.

Inventor： David P. SCHULTZ ,  Weiguang LU ,  Karthy RAJASEKHARAN ,  Shidong ZHOU ,  Michael TSIVYAN ,  Jing Jing CHEN ,  Sourabh GOYAL

IPC: G06F12/0855 ,  G06F12/0895 ,  G06F12/06 ,  G06F13/16 ,  G06F9/30

Abstract: An example configuration system for a programmable device includes: a configuration memory read/write unit configured to receive configuration data for storage in a configuration memory of the programmable device, the configuration memory comprising a plurality of frames; a plurality of configuration memory read/write controllers coupled to the configuration memory read/write unit; a plurality of fabric sub-regions (FSRs) respectively coupled to the plurality of configuration memory read/write controllers, each FSR including a pipeline of memory cells of the configuration memory disposed between buffers and a configuration memory read/write pipeline unit coupled between the pipeline and a next one of the plurality of FSRs.