公开(公告)号：US20240201863A1

公开(公告)日：2024-06-20

申请号：US18082223

申请日：2022-12-15

Applicant: XILINX, INC.

Inventor： Kumar RAHUL ,  John J. WUU ,  Santosh YACHARENI ,  Nui CHONG ,  Cheang Whang CHANG

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0629 ,  G06F3/0673

Abstract: A memory device is disclosed herein that leverages high ratio column MUXES to improve SEU resistance. The memory device may be utilized in an integrated circuit die and chip packages having the same. In one example, as semiconductor memory device is provided that includes first and second arrays of semiconductor memory cells, a plurality of sense amplifiers configured to read data states from the first and second arrays of memory cells, and a first plurality of high ratio MUXES connecting the first and second arrays of memory cells to the plurality of sense amplifiers.

公开(公告)号：US20240428848A1

公开(公告)日：2024-12-26

申请号：US18213647

申请日：2023-06-23

Applicant: XILINX, INC.

Inventor： Nui CHONG ,  Jing Jing CHEN ,  Babruwahan Tulshiram GADE ,  Shidong ZHOU

IPC: G11C11/4093 ,  G11C11/4099

Abstract: A memory device includes a first bit cell comprising a first inverter, the first inverter comprising a p-type transistor coupled to an n-type transistor, and header circuitry coupled to the first inverter and comprising a first header transistor and a second header transistor, the first header transistor having a gate configured to receive a bias voltage, the second header transistor having a gate configured to receive a reference voltage.

公开(公告)号：US20230317529A1

公开(公告)日：2023-10-05

申请号：US17712052

申请日：2022-04-01

Applicant: XILINX, INC.

Inventor： Yan WANG ,  I-Ru CHEN ,  Nui CHONG ,  Hui-Wen LIN

IPC: H01L21/66 ,  H01L21/78 ,  H01L21/321 ,  H01L23/00 ,  G01R31/28

CPC classification number: H01L22/14 ,  H01L21/78 ,  H01L21/3212 ,  H01L24/80 ,  H01L22/32 ,  G01R31/2884 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: Disclosed herein are integrated circuit (IC) structures and methods for fabricating and testing such IC structures prior to dicing from a semiconductor wafer on which the IC structures are formed. In one example, a method for fabricating an IC structure includes contacting a first plurality of test pads of the IC structure with one or more test probes. The first plurality of test pads are disposed within or on a first dielectric layer within a scribe lane, i.e., a test region. A first metal layer is formed over the first plurality of test pads if a predefined test criteria is met as determined using information obtained through first plurality of test pads using the one or more test probes. The first metal layer is a layer formed in a die region of an IC die that is being fabricated in the wafer.