公开(公告)号：US20230403021A1

公开(公告)日：2023-12-14

申请号：US17829297

申请日：2022-05-31

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS

IPC: H03M1/10

CPC classification number: H03M1/1033

Abstract: Examples describe a switched capacitor (SC) circuitry calibrated to mitigate the pole-zero (PZ) doublet errors that occur in an analog circuitry. Due to PZ-doublet errors, the slow settling time response of an input step function to an analog circuitry make it impractical to use in applications such as a digital oscilloscope. Mitigating the PZ-doublet errors in the frequency domain is not practical due to the problem of the generation of low frequency sinusoidal tones. The solution disclosed in the present invention is to apply a step function and examine the output's slow settling error waveform. A signal is input to an analog to digital converter, and the output of the converter is processed by a computation that produces calibration codes. Calibration codes are coupled to a SC circuitry to mitigate the PZ-doublet errors. The error waveform is then minimized within a specified accuracy.

公开(公告)号：US20240030898A1

公开(公告)日：2024-01-25

申请号：US17871699

申请日：2022-07-22

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS

IPC: H03H11/24 ,  H03K19/0175

CPC classification number: H03H11/245 ,  H03K19/017509

Abstract: Attenuation circuitry for a wireless receiver system receives and attenuates an input signal. The attenuation circuitry includes an input pin, coil circuitry, capacitor network circuitry, and inverter circuitry. The input pin receives the input signal. The coil circuitry is electrically connected to the input pin, receives the input signal from the input pin, and outputs an adjusted signal from the input signal. The capacitor network circuitry is electrically connected to the coil circuitry. The capacitor network circuitry receives the adjusted signal from the coil circuitry, and outputs an attenuated signal from the adjusted signal. The inverter circuitry is electrically connected to the capacitor network circuitry. The inverter circuitry receives the attenuated signal and generates an output signal from the attenuated signal. The output signal is output from the attenuation circuitry via an output inductor.

公开(公告)号：US20250105851A1

公开(公告)日：2025-03-27

申请号：US18372596

申请日：2023-09-25

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS ,  Bob W. VERBRUGGEN ,  Pedro FARIA

IPC: H03M1/06

Abstract: An analog-to-digital converter (ADC) circuitry includes channels that are interleaved with each other to generate output digital signals from input analog signals. A first channel includes sub-ADC circuitry, amplitude detection circuitry, and correction circuitry. Random chopping is applied by chopping circuitry at the input of the sub-ADC circuitry while sampling. The sub-ADC circuitry outputs digital data corresponding to the chopping states. Gain mismatch within the chopping circuitry is mitigated by determining correction values via the amplitude detection circuitry and the correction circuitry and applying the correction values to the output of the sub-ADC circuitry. The amplitude detection circuitry determines an amplitude difference between data signals. The correction circuitry is coupled to the output of the amplitude detection circuitry. The correction circuitry generates the correction values based on the amplitude difference, and outputs the correction values to adjust the data signals.

公开(公告)号：US20240056081A1

公开(公告)日：2024-02-15

申请号：US17884342

申请日：2022-08-09

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS

IPC: H03K19/0944 ,  H03K19/0185 ,  H03M1/12 ,  H03K19/0175

CPC classification number: H03K19/0944 ,  H03K19/0185 ,  H03M1/12 ,  H03K19/017545

Abstract: An electronic system includes a buffer and analog-to-digital circuitry. The buffer includes buffer circuitry that includes an input node that receives an input signal. The buffer circuitry further includes coil circuitry that is electrically connected to the input node and a first node. The coil circuitry includes a first inductor and a second inductor. Further, the buffer circuitry includes a resistor that is electrically connected to the first node and a second node. A capacitor of the buffer circuitry is electrically connected to the second node and a third node. The third node is disposed between the first inductor and the second inductor. The buffer circuitry is configured to output an output signal based on the input signal.

公开(公告)号：US20230127752A1

公开(公告)日：2023-04-27

申请号：US17511833

申请日：2021-10-27

Applicant: XILINX, INC.

Inventor： Roswald FRANCIS

IPC: H03K19/0185 ,  H03K19/00 ,  H03K19/17736 ,  H03K19/17788

Abstract: Techniques and apparatus for reducing low frequency power supply spurs in clock signals in a clock distribution network. One example circuit for clock distribution generally includes a plurality of logic inverters coupled in series and configured to drive a clock signal and a current-starved inverter coupled in parallel (or in series) with a logic inverter in the plurality of logic inverters.