公开(公告)号：US20250004983A1

公开(公告)日：2025-01-02

申请号：US18215668

申请日：2023-06-28

Applicant: XILINX, INC.

Inventor： Brian C. GAIDE ,  Sneha Bhalchandra DATE ,  Juan J. NOGUERA SERRA

IPC: G06F15/80

Abstract: Examples herein describe a three-dimensional (3D) die stack. The 3D die stack includes a programmable logic (PL) die and a compute die stacked on top of the PL die. The PL die includes a plurality of configurable blocks and a plurality of first electrical connections on a top side of the PL die. The compute die includes a plurality of data processing engines and a plurality of second electrical connections on a bottom side of the compute die. The three-dimensional die stack includes a plurality of tiles, each tile comprising M configurable blocks included in the plurality of configurable blocks and N data processing engines included in the plurality of data processing engines.

公开(公告)号：US20240256482A1

公开(公告)日：2024-08-01

申请号：US18633398

申请日：2024-04-11

Applicant: XILINX, INC.

Inventor： Juan J. NOGUERA SERRA ,  Sneha Bhalchandra DATE ,  Jan LANGER ,  Baris OZGUL ,  Goran Hk BILSKI

IPC: G06F15/177 ,  G06F9/4401 ,  G06F15/173 ,  G06F15/80

CPC classification number: G06F15/177 ,  G06F15/17306 ,  G06F15/80 ,  G06F9/4401 ,  G06F9/4411

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US20230205726A1

公开(公告)日：2023-06-29

申请号：US18114850

申请日：2023-02-27

Applicant: XILINX, INC.

Inventor： Juan J. NOGUERA SERRA ,  Sneha Bhalchandra DATE ,  Jan LANGER ,  Baris OZGUL ,  Goran H.k. BILSKI

IPC: G06F15/177 ,  G06F15/173 ,  G06F15/80

CPC classification number: G06F15/177 ,  G06F15/17306 ,  G06F15/80 ,  G06F9/4401

Abstract: A device may include a processor system and an array of data processing engines (DPEs) communicatively coupled to the processor system. Each of the DPEs includes a core and a DPE interconnect. The processor system is configured to transmit configuration data to the array of DPEs, and each of the DPEs is independently configurable based on the configuration data received at the respective DPE via the DPE interconnect of the respective DPE. The array of DPEs enable, without modifying operation of a first kernel of a first subset of the DPEs of the array of DPEs, reconfiguration of a second subset of the DPEs of the array of DPEs.

公开(公告)号：US20220283985A1

公开(公告)日：2022-09-08

申请号：US17826070

申请日：2022-05-26

Applicant: XILINX, INC.

Inventor： Goran Hk BILSKI ,  Juan J. NOGUERA SERRA ,  Baris OZGUL ,  Jan LANGER ,  David CLARKE ,  Sneha Bhalchandra DATE

IPC: G06F15/80 ,  G06F13/40 ,  G06F15/173 ,  G06F13/16

Abstract: An example data processing engine (DPE) for a DPE array in an integrated circuit (IC) includes: a core; a memory including a data memory and a program memory, the program memory coupled to the core, the data memory coupled to the core and including at least one connection to a respective at least one additional core external to the DPE; support circuitry including hardware synchronization circuitry and direct memory access (DMA) circuitry each coupled to the data memory; streaming interconnect coupled to the DMA circuitry and the core; and memory-mapped interconnect coupled to the core, the memory, and the support circuitry.