公开(公告)号：US12068257B1

公开(公告)日：2024-08-20

申请号：US17136721

申请日：2020-12-29

Applicant: XILINX, INC.

Inventor： Myongseob Kim ,  Henley Liu ,  Yun Wu ,  Cheang Whang Chang

IPC: H01L23/552 ,  H01L21/50 ,  H01L23/528

CPC classification number: H01L23/552 ,  H01L21/50 ,  H01L23/528

Abstract: Some examples described herein relate to protecting an integrated circuit (IC) structure from imaging or access. In an example, an IC structure includes a semiconductor substrate, an electromagnetic radiation blocking layer, and a support substrate. The semiconductor substrate has a circuit disposed on a front side of the semiconductor substrate. The electromagnetic radiation blocking layer is disposed on a backside of the semiconductor substrate opposite from the front side of the semiconductor substrate. The support substrate is bonded to the semiconductor substrate. The electromagnetic radiation blocking layer is disposed between the semiconductor substrate and the support substrate.

公开(公告)号：US09385127B2

公开(公告)日：2016-07-05

申请号：US13973616

申请日：2013-08-22

Applicant: Xilinx, Inc.

Inventor： Qi Lin ,  Hong-Tsz Pan ,  Yun Wu ,  Bang-Thu Nguyen

IPC: H01L21/70 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/8238 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/092

Abstract: An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.

Abstract translation: 反相器包括：PMOS，包括：p型源极区域，p型漏极区域，p型源极区域和p型漏极区域之间的p沟道区域以及PMOS金属栅极区域; NMOS，包括：n型源极区域，n型漏极区域，n型源极区域和n型漏极区域之间的n沟道区域以及NMOS金属栅极区域; 在p沟道区域和n沟道区域上方的绝缘层，其中PMOS金属栅极区域和NMOS金属栅极区域在绝缘层之上; 以及NMOS金属栅极区域和PMOS金属栅极区域之间的栅极接触。

公开(公告)号：US20150054085A1

公开(公告)日：2015-02-26

申请号：US13973616

申请日：2013-08-22

Applicant: Xilinx, Inc.

Inventor： Qi Lin ,  Hong-Tsz Pan ,  Yun Wu ,  Bang-Thu Nguyen

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/8238 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/092

Abstract: An inverter includes: a PMOS comprising: a p-type source region, a p-type drain region, a p-channel region between the p-type source region and the p-type drain region, and a PMOS metal gate region; a NMOS, comprising: an n-type source region, an n-type drain region, an n-channel region between the n-type source region and the n-type drain region, and a NMOS metal gate region; an insulating layer above the p-channel region and the n-channel region, wherein the PMOS metal gate region and the NMOS metal gate region are above the insulating layer; and a gate contact between the NMOS metal gate region and the PMOS metal gate region.

Abstract translation: 反相器包括：PMOS，包括：p型源极区域，p型漏极区域，p型源极区域和p型漏极区域之间的p沟道区域以及PMOS金属栅极区域; NMOS，包括：n型源极区域，n型漏极区域，n型源极区域和n型漏极区域之间的n沟道区域以及NMOS金属栅极区域; 在p沟道区域和n沟道区域上方的绝缘层，其中PMOS金属栅极区域和NMOS金属栅极区域在绝缘层之上; 以及NMOS金属栅极区域和PMOS金属栅极区域之间的栅极接触。