公开(公告)号：US11256520B2

公开(公告)日：2022-02-22

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F11/00 ,  G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US20210081215A1

公开(公告)日：2021-03-18

申请号：US16574956

申请日：2019-09-18

Applicant: Xilinx, Inc.

Inventor： David P. Schultz ,  Adrian M. Hernandez ,  David Robinson ,  Elessar Taggart ,  Max Heimer

IPC: G06F9/445 ,  G06F11/07

Abstract: Tracing status of a programmable device can include, in response to loading a device image for the programmable device, determining, using a processing unit on the programmable device, trace data for the device image, storing, by the processing unit, the trace data for the device image in a memory, and, in response to unloading the device image, recording the unloading of the device image in the trace data in the memory.

公开(公告)号：US09639646B2

公开(公告)日：2017-05-02

申请号：US14338155

申请日：2014-07-22

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Adrian M. Hernandez

IPC: G06F9/455 ,  G06F17/50 ,  H03K19/177 ,  G11C5/02

CPC classification number: G06F17/5068 ,  G06F17/5054 ,  G06F2217/66 ,  G11C5/025 ,  H03K19/17728

Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

公开(公告)号：US20160026742A1

公开(公告)日：2016-01-28

申请号：US14338155

申请日：2014-07-22

Applicant: Xilinx, Inc.

Inventor： Graham F. Schelle ,  Paul R. Schumacher ,  Adrian M. Hernandez

IPC: G06F17/50 ,  H03K19/177 ,  G11C7/10

CPC classification number: G06F17/5068 ,  G06F17/5054 ,  G06F2217/66 ,  G11C5/025 ,  H03K19/17728

Abstract: An integrated circuit (IC) includes a bridge circuit configured to receive a first request from an external system, a discover circuit coupled to the bridge circuit and configured to process the first request received from the bridge circuit, and a memory map coupled to the discover circuit. The memory map stores a record for each of a plurality of Intellectual Property (IP) blocks implemented within the IC. The discover circuit is configured to generate a list of the IP blocks implemented within the IC from the records of the memory map responsive to the first request. The bridge circuit is configured to send the list to the external system.

Abstract translation: 集成电路（IC）包括被配置为从外部系统接收第一请求的桥接电路，耦合到桥接电路并被配置为处理从桥接电路接收的第一请求的发现电路以及耦合到发现的存储器映射 电路。 存储器映射存储在IC内实现的多个知识产权（IP）块中的每一个的记录。 发现电路被配置为响应于第一请求从存储器映射的记录生成在IC内实现的IP块的列表。 桥接电路配置为将列表发送到外部系统。