公开(公告)号：US09509640B2

公开(公告)日：2016-11-29

申请号：US14561452

申请日：2014-12-05

Applicant: Xilinx, Inc.

Inventor： David F. Taylor ,  Matthew H. Klein ,  Vincent Vendramini

IPC: H04K1/10 ,  G11C7/00 ,  H04L12/861 ,  H03L7/06 ,  G06F5/10 ,  G06F5/06 ,  H03M9/00 ,  G06F5/12

CPC classification number: H04L49/90 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G06F2205/126 ,  H03L7/06 ,  H03L7/07 ,  H03M9/00

Abstract: In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Abstract translation: 在缓冲方法中，缓冲器缓冲响应于读和写时钟信号的数据。 来自缓冲器的标志信号用于其填充水平。 响应于缓冲的数据高于或低于填充水平的设定点，该标志信号被切换。 响应于标志信号的切换，写时钟信号的相位被调整为读时钟信号的相位。 写时钟信号用于控制缓冲器的延迟。 写时钟信号的相位的调整包括：响应于标志信号的切换产生超控信号; 并将读取的时钟信号和超控信号输入到相位调节器，以在操作期间将写时钟信号的相位可控地调节到读时钟信号的相位。

公开(公告)号：US20160164665A1

公开(公告)日：2016-06-09

申请号：US14561452

申请日：2014-12-05

Applicant: Xilinx, Inc.

Inventor： David F. Taylor ,  Matthew H. Klein ,  Vincent Vendramini

IPC: H04L7/033 ,  H03L7/06 ,  H04L12/861 ,  H03H11/20

CPC classification number: H04L49/90 ,  G06F5/06 ,  G06F5/10 ,  G06F5/12 ,  G06F2205/126 ,  H03L7/06 ,  H03L7/07 ,  H03M9/00

Abstract: In a method for buffering, a buffer buffers data responsive to read and write clock signals. A flag signal from the buffer is for a fill level thereof. The flag signal is toggled responsive to the data buffered being either above or below a set point for the fill level. A phase of the write clock signal is adjusted to a phase of the read clock signal responsive to the toggling of the flag signal. The write clock signal is used to control latency of the buffer. The adjusting of the phase of the write clock signal includes: generating an override signal responsive to the toggling of the flag signal; and inputting the read clock signal and the override signal to a phase adjuster to controllably adjust the phase of the write clock signal to the phase of the read clock signal during operation.

Abstract translation: 在缓冲方法中，缓冲器缓冲响应于读和写时钟信号的数据。 来自缓冲器的标志信号用于其填充水平。 响应于缓冲的数据高于或低于填充水平的设定点，该标志信号被切换。 响应于标志信号的切换，写时钟信号的相位被调整为读时钟信号的相位。 写时钟信号用于控制缓冲器的延迟。 写时钟信号的相位的调整包括：响应于标志信号的切换产生超控信号; 并将读取的时钟信号和超控信号输入到相位调节器，以在操作期间将写时钟信号的相位可控地调节到读时钟信号的相位。

公开(公告)号：US10547317B1

公开(公告)日：2020-01-28

申请号：US16458859

申请日：2019-07-01

Applicant: Xilinx, Inc.

Inventor： Paolo Novellini ,  David F. Taylor ,  Alastair J. Richardson

IPC: H03L7/085 ,  H04B1/08 ,  H03L7/099

Abstract: A device includes a physical medium attachment (PMA), a physical coding sublayer (PCS), a phase detector, and an oscillator. The PMA receives data at a first speed and overclocks the received data to a second speed, wherein the second speed is higher than the first speed. The PCS receives the data at the second speed. The phase detector receives another data from the PCS wherein the another data is based on the received data at the second speed or the phase detector is configured to receive the data at the second speed directly from the PMA. The phase detector adjusts a phase based on bit transitions. The oscillator is coupled to the phase detector and generates a reference clock signal wherein a phase of the reference clock is adjusted by the phase detector. The oscillator clocks the PMA based on the adjusted clock.

公开(公告)号：US09787313B1

公开(公告)日：2017-10-10

申请号：US15159155

申请日：2016-05-19

Applicant: Xilinx, Inc.

Inventor： Matthew H. Klein ,  David F. Taylor

IPC: G04C21/28 ,  H03L7/06 ,  H03K5/135 ,  H03M9/00 ,  H03K5/00

CPC classification number: H03L7/06 ,  H03K5/135 ,  H03K2005/00052 ,  H03L7/16 ,  H03M9/00

Abstract: An example pulse generation circuit includes a parallel-to-serial circuit configured to convert parallel data to serial data according to parallel clock signal and a serial clock signal, the serial data comprises a sequence of pulses; a clock generator configured to generate a clock signal; and a phase controller configured to generate the serial clock signal from the clock signal based on a phase control signal.