公开(公告)号：US20230113197A1

公开(公告)日：2023-04-13

申请号：US17498048

申请日：2021-10-11

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Tharun Kumar Ksheerasagar ,  Hemant Kashyap ,  Madhusudana Reddy ,  Rohit Bhadana

IPC: G06F30/3308 ,  G06F30/323

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.

公开(公告)号：US12086521B2

公开(公告)日：2024-09-10

申请号：US17496198

申请日：2021-10-07

Applicant: Xilinx, Inc.

Inventor： Tharun Kumar Ksheerasagar ,  Rohit Bhadana ,  Hemant Kashyap ,  Pratyush Ranjan

IPC: G06F30/3312 ,  G06F30/327 ,  G06F119/12

CPC classification number: G06F30/3312 ,  G06F30/327 ,  G06F2119/12

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.

公开(公告)号：US11630935B1

公开(公告)日：2023-04-18

申请号：US17498048

申请日：2021-10-11

Applicant: Xilinx, Inc.

Inventor： Amit Kasat ,  Tharun Kumar Ksheerasagar ,  Hemant Kashyap ,  Madhusudana Reddy ,  Rohit Bhadana

IPC: G06F30/30 ,  G01R31/28 ,  G06F30/3308 ,  G06F30/323 ,  G01R31/3183

Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server. The communication layer client provides an application programming interface through which an external computer program generates data traffic to drive the DUT within the simulation.

公开(公告)号：US12032932B2

公开(公告)日：2024-07-09

申请号：US17811660

申请日：2022-07-11

Applicant: Xilinx, Inc.

Inventor： Shantanu Mishra ,  Hemant Kashyap ,  Uday Kyatham ,  Mahesh Attarde ,  Amit Kasat Kasat

IPC: G06F8/41

CPC classification number: G06F8/434 ,  G06F8/44

Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

公开(公告)号：US20240012629A1

公开(公告)日：2024-01-11

申请号：US17811660

申请日：2022-07-11

Applicant: Xilinx, Inc.

Inventor： Shantanu Mishra ,  Hemant Kashyap ,  Uday Kyatham ,  Mahesh Attarde ,  Amit Kasat Kasat

IPC: G06F8/41

CPC classification number: G06F8/434 ,  G06F8/44

Abstract: Compiling a high-level synthesis circuit design for simulation includes analyzing, using computer hardware, a kernel specified in a high-level language to detect pointers therein. A determination is made as to which of the pointers are global address space pointers referencing a global address space. The kernel is instrumented by replacing accesses in the kernel to the global address space with calls to wrapper functions for performing the accesses. A simulation kernel is generated that specifies an assembly language version of the kernel as instrumented.

公开(公告)号：US20240184616A1

公开(公告)日：2024-06-06

申请号：US18075731

申请日：2022-12-06

Applicant: Xilinx, Inc.

Inventor： Tharun Kumar Ksheerasagar ,  Hemant Kashyap ,  Amit Kasat ,  Meghana Tripathi ,  Shantanu Mishra

IPC: G06F9/48 ,  G06F9/455

CPC classification number: G06F9/48 ,  G06F9/455

Abstract: A thread manager creates multiple threads by to execute a simulation of subsystems of a system-on-chip on multiple processor cores in response to execution of a simulation program. The threads execute multiple cycle-accurate simulation models of the subsystems in parallel in an execution phase of each simulation cycle of a plurality of simulation cycles of the simulation. The threads update interfaces of the simulation models in an update phase of each simulation cycle of the plurality of simulation cycles.

公开(公告)号：US20230114858A1

公开(公告)日：2023-04-13

申请号：US17496198

申请日：2021-10-07

Applicant: Xilinx, Inc.

Inventor： Tharun Kumar Ksheerasagar ,  Rohit Bhadana ,  Hemant Kashyap ,  Pratyush Ranjan

IPC: G06F30/3312 ,  G06F30/327

Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.