公开(公告)号：US20200151120A1

公开(公告)日：2020-05-14

申请号：US16186055

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Ravi N. Kurlaganda ,  Kenneth K. Chan ,  Ravi Sunkavalli

IPC: G06F13/16 ,  G06F13/40 ,  G06F9/30

Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

公开(公告)号：US10924430B2

公开(公告)日：2021-02-16

申请号：US16186102

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Hem C. Neema ,  Kenneth K. Chan ,  Ravi N. Kurlagunda ,  Karen Xie ,  Sonal Santan ,  Lizhi Hou

IPC: H04L12/933 ,  H04L12/861 ,  G06F13/16 ,  G06F13/28

Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

公开(公告)号：US10725942B2

公开(公告)日：2020-07-28

申请号：US16186055

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Ravi N. Kurlagunda ,  Kenneth K. Chan ,  Ravi Sunkavalli

IPC: G06F13/40 ,  G06F13/16 ,  G06F9/30

Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

公开(公告)号：US20200153756A1

公开(公告)日：2020-05-14

申请号：US16186102

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Hem C. Neema ,  Kenneth K. Chan ,  Ravi N. Kurlaganda ,  Karen Xie ,  Sonal Santan ,  Lizhi Hou

IPC: H04L12/933 ,  H04L12/861 ,  G06F13/28 ,  G06F13/16

Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.