公开(公告)号：US11144652B1

公开(公告)日：2021-10-12

申请号：US16721550

申请日：2019-12-19

Applicant: Xilinx, Inc.

Inventor： Ellery Cochell ,  Brian S. Martin ,  Ravi N. Kurlagunda

IPC: G06F21/60 ,  G06F21/79 ,  H04L9/08 ,  H04L29/06 ,  G06F21/57

Abstract: Secure updating of programmable integrated circuits includes receiving, within the programmable integrated circuit, a configuration bitstream, inserting, using a processor of the programmable integrated circuit, a key into the configuration bitstream resulting in a modified configuration bitstream, encrypting, using the programmable integrated circuit, the modified configuration bitstream using the key resulting in an encrypted configuration bitstream, and storing the encrypted configuration bitstream in a boot memory for the programmable integrated circuit.

公开(公告)号：US20210042252A1

公开(公告)日：2021-02-11

申请号：US16537605

申请日：2019-08-11

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Ravi Sunkavalli ,  Ravi N. Kurlagunda ,  Ellery Cochell

IPC: G06F13/28 ,  G06F17/50

Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.

公开(公告)号：US11386034B2

公开(公告)日：2022-07-12

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US20220138140A1

公开(公告)日：2022-05-05

申请号：US17085740

申请日：2020-10-30

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Ravi N. Kurlagunda ,  Min Ma ,  Himanshu Choudhary ,  Manjunath Chepuri ,  Cheng Zhen ,  Pranjal Joshi ,  Sebastian Turullols ,  Amit Kumar ,  Kaustuv Manji ,  Ravinder Sharma ,  Ch Vamshi Krishna

IPC: G06F13/42

Abstract: A hardware acceleration device can include a switch communicatively linked to a host central processing unit (CPU), an adapter coupled to the switch via a control bus, wherein the control bus is configured to convey addresses of descriptors from the host central CPU to the adapter, and a random-access memory (RAM) coupled to the switch through a data bus. The RAM is configured to store descriptors received from the host CPU via the data bus. The hardware acceleration device can include a compute unit coupled to the adapter and configured to perform operations specified by the descriptors. The adapter may be configured to retrieve the descriptors from the RAM via the data bus, provide arguments from the descriptors to the compute unit, and provide control signals to the compute unit to initiate the operations using the arguments.

公开(公告)号：US11055106B1

公开(公告)日：2021-07-06

申请号：US16719449

申请日：2019-12-18

Applicant: Xilinx, Inc.

Inventor： Ellery Cochell ,  Brian S. Martin ,  Chandrasekhar S. Thyamagondlu ,  Ravi N. Kurlagunda

IPC: G06F9/4401 ,  G06F21/57 ,  G06F13/28

Abstract: Bootstrapping a programmable integrated circuit (IC) based network interface card (NIC) can include implementing, within the programmable IC, a first circuitry by loading a first stage configuration bitstream, wherein the first circuitry includes a bus endpoint configured to communicate with a host computer via a communication bus, a platform processor, and a first bootloader. The platform processor, executing the first bootloader, loads a first firmware within the programmable IC. A second circuitry is implemented within the programmable IC by the platform processor executing the first firmware to load a second stage configuration bitstream. The second circuitry includes a NIC controller. The platform processor, executing the first firmware, loads a second firmware within the programmable IC. The second firmware is executable to configure the second circuitry.

公开(公告)号：US10990547B2

公开(公告)日：2021-04-27

申请号：US16537605

申请日：2019-08-11

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Ravi Sunkavalli ,  Ravi N. Kurlagunda ,  Ellery Cochell

IPC: G06F13/28 ,  G06F30/34

Abstract: A device includes a platform implemented, at least in part, in a static region of programmable circuitry and a dynamic region of programmable circuitry configured to implement user-specified circuitry in communication with the platform. The platform is configured to establish and maintain a first communication link with a host data processing system and a second communication link with a network while at least a portion of the dynamic region of programmable circuitry is dynamically reconfigured.

公开(公告)号：US10924430B2

公开(公告)日：2021-02-16

申请号：US16186102

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Hem C. Neema ,  Kenneth K. Chan ,  Ravi N. Kurlagunda ,  Karen Xie ,  Sonal Santan ,  Lizhi Hou

IPC: H04L12/933 ,  H04L12/861 ,  G06F13/16 ,  G06F13/28

Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

公开(公告)号：US10725942B2

公开(公告)日：2020-07-28

申请号：US16186055

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Ravi N. Kurlagunda ,  Kenneth K. Chan ,  Ravi Sunkavalli

IPC: G06F13/40 ,  G06F13/16 ,  G06F9/30

Abstract: An integrated circuit (IC) includes a first kernel circuit implemented in programmable circuitry, a second kernel circuit implemented in programmable circuitry, and a stream traffic manager circuit coupled to the first kernel circuit and the second kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the first kernel circuit and the second kernel circuit.

公开(公告)号：US09679092B1

公开(公告)日：2017-06-13

申请号：US14931650

申请日：2015-11-03

Applicant: Xilinx, Inc.

Inventor： Pradip K. Jha ,  Ravi N. Kurlagunda ,  David A. Knol ,  Dinesh K. Monga ,  Stephen P. Rozum ,  Sudipto Chakraborty

IPC: G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5022 ,  G06F17/5031 ,  G06F17/504 ,  G06F17/505 ,  G06F2217/84

Abstract: Constraint handling for a circuit design may include determining, using a processor, instances of parameterizable modules of a circuit design associated with constraints based upon a predefined hardware description language attribute within the instances, extracting, using the processor, parameter values from the instances of the parameterizable modules, and generating, using the processor, static constraint files for the instances of the parameterizable modules using the extracted parameter values.