公开(公告)号：US11922223B1

公开(公告)日：2024-03-05

申请号：US17170427

申请日：2021-02-08

Applicant: Xilinx, Inc.

Inventor： Adam P. Donlin ,  Kyle Corbett ,  Lizhi Hou ,  Julian M. Kain

IPC: G06F9/50 ,  G06F9/38 ,  H04L9/06

CPC classification number: G06F9/5077 ,  G06F9/3836 ,  G06F9/3877 ,  H04L9/0643

Abstract: Control of a reconfigurable platform can include determining, by a host computer, an interface universally unique identifier (UUID) of an interface of platform circuitry implemented on an accelerator, wherein the accelerator is communicatively linked to the host computer. An electronic request to run a partition design on the accelerator is received by the host computer. In response to the electronic request, the host computer determines an interface UUID for an interface of the partition design and determines compatibility of the partition design with the platform circuitry based on a comparison of the interface UUID of the partition design with the interface UUID of the platform circuitry. The partition design is implemented on the accelerator in response to determining that the partition design is compatible with the platform circuitry.

公开(公告)号：US11861010B2

公开(公告)日：2024-01-02

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/64 ,  G06F21/71 ,  G06F21/57 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F13/1642 ,  G06F13/1663 ,  G06F21/64 ,  G06F21/71

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

公开(公告)号：US20230259627A1

公开(公告)日：2023-08-17

申请号：US17651030

申请日：2022-02-14

Applicant: Xilinx, Inc.

Inventor： Sonal Santan ,  Yu Liu ,  Yenpang Lin ,  Lizhi Hou ,  Cheng Zhen ,  Yidong Zhang

IPC: G06F21/57 ,  G06F21/64 ,  G06F21/71 ,  G06F13/16

CPC classification number: G06F21/572 ,  G06F21/64 ,  G06F21/71 ,  G06F13/1642 ,  G06F13/1663

Abstract: An integrated circuit can include a communication endpoint configured to maintain a communication link with a host computer, a queue configured to receive a plurality of host commands from the host computer via the communication link, and a processor configured to execute a device runtime. The processor, responsive to executing the device runtime, is configured to perform validation of the host commands read from the queue and selectively execute the host commands based on a result of the validation on a per host command basis. The host commands are executable by the processor to manage functions of the integrated circuit. The queue is implemented in a region of memory that is shared by the integrated circuit and the host computer.

公开(公告)号：US11163605B1

公开(公告)日：2021-11-02

申请号：US16571776

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Sonal Santan ,  Min Ma ,  Soren Soe ,  Cheng Zhen ,  Lizhi Hou ,  Yu Liu

IPC: G06F9/46 ,  G06F9/48

Abstract: Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.

公开(公告)号：US10924430B2

公开(公告)日：2021-02-16

申请号：US16186102

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Hem C. Neema ,  Kenneth K. Chan ,  Ravi N. Kurlagunda ,  Karen Xie ,  Sonal Santan ,  Lizhi Hou

IPC: H04L12/933 ,  H04L12/861 ,  G06F13/16 ,  G06F13/28

Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.

公开(公告)号：US20200153756A1

公开(公告)日：2020-05-14

申请号：US16186102

申请日：2018-11-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Hem C. Neema ,  Kenneth K. Chan ,  Ravi N. Kurlaganda ,  Karen Xie ,  Sonal Santan ,  Lizhi Hou

IPC: H04L12/933 ,  H04L12/861 ,  G06F13/28 ,  G06F13/16

Abstract: A system includes a host system and an integrated circuit coupled to the host system through a communication interface. The integrated circuit is configured for hardware acceleration. The integrated circuit includes a direct memory access circuit coupled to the communication interface, a kernel circuit, and a stream traffic manager circuit coupled to the direct memory access circuit and the kernel circuit. The stream traffic manager circuit is configured to control data streams exchanged between the host system and the kernel circuit.