公开(公告)号：US11726936B2

公开(公告)日：2023-08-15

申请号：US17457576

申请日：2021-12-03

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Ravi Sunkavalli ,  Akhil Krishnan ,  Tao Yu ,  Kushagra Sharma

IPC: G06F13/28 ,  G06F13/24

CPC classification number: G06F13/28 ,  G06F13/24

Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

公开(公告)号：US10657084B1

公开(公告)日：2020-05-19

申请号：US16183646

申请日：2018-11-07

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Tao Yu ,  Kushagra Sharma ,  Tuan Van-Dinh

IPC: G06F13/24 ,  G06F13/28

Abstract: A memory circuit is configured for storage of completion queues. Each completion queue can store completion descriptors associated with transfers of data from interrupt source circuits to the memory circuit. A direct memory access circuit provides access to the memory circuit for the interrupt source circuits. An interrupt engine issues interrupt messages for processing the completion descriptors in the completion queues in response to satisfaction of a set of trigger conditions specified in an active interrupt moderation mode. The active interrupt moderation mode is one of multiple available interrupt moderation modes. The interrupt engine bypasses issuing interrupt messages in response to the set of trigger conditions of the active interrupt moderation mode not being satisfied.

公开(公告)号：US20250004961A1

公开(公告)日：2025-01-02

申请号：US18344783

申请日：2023-06-29

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Kushagra Sharma ,  Surender Reddy Kisanagar

IPC: G06F13/28

Abstract: A direct memory access (DMA) system includes a read request circuit configured to receive read requests from a plurality of client circuits. The DMA system includes a response reassembly circuit configured to reorder read completion data received from a plurality of different hosts in response to the read requests. The DMA system includes a read scheduler circuit configured to schedule conveyance of the read completion data from the response reassembly circuit to the plurality of client circuits. The DMA system includes a data pipeline circuit implementing a plurality of data paths coupled to respective ones of the plurality of client circuits for conveying the read completion data as scheduled by the read scheduler circuit.

公开(公告)号：US20220092010A1

公开(公告)日：2022-03-24

申请号：US17457576

申请日：2021-12-03

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Ravi Sunkavalli ,  Akhil Krishnan ,  Tao Yu ,  Kushagra Sharma

IPC: G06F13/28 ,  G06F13/24

Abstract: A system can include a plurality of processors. Each processor of the plurality of processors can be configured to execute program code. The system can include a direct memory access system configured for multi-processor operation. The direct memory access system can include a plurality of data engines coupled to a plurality of interfaces via a plurality of switches. The plurality of switches can be programmable to couple different ones of the plurality of data engines to different ones of the plurality of processors for performing direct memory access operations based on a plurality of host profiles corresponding to the plurality of processors.

公开(公告)号：US11232053B1

公开(公告)日：2022-01-25

申请号：US16896765

申请日：2020-06-09

Applicant: Xilinx, Inc.

Inventor： Chandrasekhar S. Thyamagondlu ,  Darren Jue ,  Ravi Sunkavalli ,  Akhil Krishnan ,  Tao Yu ,  Kushagra Sharma

IPC: G06F13/28 ,  G06F13/24

Abstract: A direct memory access (DMA) system can include a memory configured to store a plurality of host profiles, a plurality of interfaces, wherein two or more of the plurality of interfaces correspond to different ones of a plurality of host processors, and a plurality of data engines coupled to the plurality of interfaces. The plurality of data engines are independently configurable to access different ones of the plurality of interfaces for different flows of a DMA operation based on the plurality of host profiles.