公开(公告)号：US20200372123A1

公开(公告)日：2020-11-26

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F17/50

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.

公开(公告)号：US11176296B1

公开(公告)日：2021-11-16

申请号：US17007177

申请日：2020-08-31

Applicant: Xilinx, Inc.

Inventor： Pradip Jha ,  Brendan Matthew O'Higgins ,  Dinesh K. Monga ,  Bart Reynolds ,  Ryan Linderman

IPC: G06F30/30 ,  G06F30/327 ,  G06F30/33 ,  G06F9/451 ,  G06F15/78 ,  G06F30/39

Abstract: A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.

公开(公告)号：US10891414B2

公开(公告)日：2021-01-12

申请号：US16421443

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Srinivas Beeravolu ,  Dinesh K. Monga ,  Pradip Jha ,  Vishal Suthar ,  Vinod K. Kathail ,  Vidhumouli Hunsigida ,  Siddarth Rele

IPC: G06F30/34

Abstract: For an application specifying a software portion for implementation within a data processing engine (DPE) array of a device and a hardware portion for implementation within programmable logic (PL) of the device, a logical architecture for the application and a first interface solution specifying a mapping of logical resources to hardware of an interface circuit block between the DPE array and the programmable logic are generated. A block diagram of the hardware portion is built based on the logical architecture and the first interface solution. An implementation flow is performed on the block diagram. The software portion of the application is compiled for implementation in one or more DPEs of the DPE array.