公开(公告)号：US10331837B1

公开(公告)日：2019-06-25

申请号：US15354894

申请日：2016-11-17

Applicant: Xilinx, Inc.

Inventor： Jennifer D. McEwen ,  Ian L. McEwen ,  Chong M. Lee ,  Bart Reynolds

IPC: G06F17/50 ,  G06T11/20 ,  G06T11/60

Abstract: Rendering a graphical representation of an integrated circuit can include determining, using a processor, a tile of a device model at least partially within a viewport, determining, using the processor, an owning tile having a fly-over wire passing over the tile, determining, using the processor, a predetermined shape of the fly-over wire, and drawing, using the processor, the fly-over wire within the viewport based upon the shape.

公开(公告)号：US10956638B1

公开(公告)日：2021-03-23

申请号：US16514324

申请日：2019-07-17

Applicant: XILINX, INC.

Inventor： Bart Reynolds ,  Xiaojian Yang ,  Matthew H. Klein

IPC: G06F30/331 ,  G06F30/392 ,  G06F30/398

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.

公开(公告)号：US11176296B1

公开(公告)日：2021-11-16

申请号：US17007177

申请日：2020-08-31

Applicant: Xilinx, Inc.

Inventor： Pradip Jha ,  Brendan Matthew O'Higgins ,  Dinesh K. Monga ,  Bart Reynolds ,  Ryan Linderman

IPC: G06F30/30 ,  G06F30/327 ,  G06F30/33 ,  G06F9/451 ,  G06F15/78 ,  G06F30/39

Abstract: A unified data model for creating a circuit design for a heterogeneous integrated circuit is provided. The unified data model is stored as a data structure in computer hardware. The unified data model includes a unified netlist specifying the circuit design and a unified device model representing the heterogeneous integrated circuit. The unified netlist includes netlist objects configured to communicate over bitwise connections and network connections representing packet-based communications. The unified netlist may be mapped to the unified device model using computer hardware. Using the computer hardware, at least a portion of the device model may be displayed in coordination with at least a portion of the unified netlist mapped thereto.

公开(公告)号：US10402521B1

公开(公告)日：2019-09-03

申请号：US15410597

申请日：2017-01-19

Applicant: Xilinx, Inc.

Inventor： Bart Reynolds ,  Xiaojian Yang ,  Matthew H. Klein

IPC: G06F17/50

Abstract: Methods and apparatus are described for providing and using programmable ICs suitable for meeting the unique desires of large hardware emulation systems. One example method of classifying a programmable IC having impaired circuitry generally includes determining a partitioning of programmable logic resources into two or more groups for classifying the programmable IC, testing the programmable IC to determine at least one location of the impaired circuitry in the programmable logic resources of the programmable IC, and classifying the programmable IC based on the at least one location of the impaired circuitry in relation to the partitioning of the programmable logic resources.