公开(公告)号：US10671785B1

公开(公告)日：2020-06-02

申请号：US15370339

申请日：2016-12-06

Applicant: Xilinx, Inc.

Inventor： Valeria Mihalache ,  Kumar Deepak ,  Saikat Bandyopadhyay ,  Sandeep S. Deshpande ,  Feng Cai

IPC: G06F30/367

Abstract: Simulating a hardware description language design including a core and a testbench can include performing, using a processor, a first compilation of the hardware description language design by generating a compiled core unit for the core, a compiled testbench for the testbench, and synchronization data describing signals crossing a compile checkpoint boundary. A subsequent compilation of the hardware description language design can be performed by reusing the compiled core unit from the first compilation and generating a new compiled testbench for the testbench using the synchronization data.

公开(公告)号：US20240012973A1

公开(公告)日：2024-01-11

申请号：US17862061

申请日：2022-07-11

Applicant: Xilinx, Inc.

Inventor： Sandeep S. Deshpande ,  Saikat Bandyopadhyay

IPC: G06F30/367

CPC classification number: G06F30/367

Abstract: Simulation of a waveform in a circuit simulation includes preparing, in response to a programming interface call by a testbench, a schedule of states of a signal at two or more intervals in the simulation by a simulator. The programming interface call specifies a sequence of the states and indicates durations of the states during the simulation. The signal is set to a first state of the sequence by the simulator during the simulation and then to a second state of the sequence according to the schedule.

公开(公告)号：US10726182B1

公开(公告)日：2020-07-28

申请号：US16100041

申请日：2018-08-09

Applicant: Xilinx, Inc.

Inventor： Sandeep S. Deshpande ,  Feng Cai ,  Saikat Bandyopadhyay

IPC: G06F17/50 ,  G06F30/3312 ,  G06F9/448 ,  G06F30/327

Abstract: Disclosed approaches involve simulating a circuit design specified in a hardware description language (HDL). During simulation, a thread is started at an edge of a simulation clock signal for evaluation of states of a finite state machine (FSM) that represent a series of events specified in a statement in the HDL. The thread transitions from one state to a next state in the FSM in response to evaluation of the one state. In response to encountering a fork state in the FSM, the thread is forked into two threads during simulation. The fork state represents a composite operator in the statement, and the FSM has a branch from the fork state for each operand of the composite operator. In response to encountering a join state in the FSM by the two threads, the two threads are joined into one thread.