公开(公告)号：US09824170B1

公开(公告)日：2017-11-21

申请号：US14989676

申请日：2016-01-06

Applicant: Xilinx, Inc.

Inventor： Alec J. Wong ,  Pradip K. Jha ,  Steven Banks ,  Sudipto Chakraborty ,  Dennis McCrohan

IPC: G06F17/00 ,  G06F17/50

CPC classification number: G06F17/5045 ,  G06F17/5068

Abstract: Message filtering may include, during a first processing phase of a design specified in source code, creating a filter table including message filters and storing the filter table in a memory using a processor. Each message filter may specify a message criterion and an object identifier of the design. During a subsequent processing phase of the design, received messages may be compared with the message filters of the filter table using the processor. Responsive to determining that a selected message matches a message criterion and an object identifier of a selected message filter, the message may be suppressed using the processor.

公开(公告)号：US09864830B1

公开(公告)日：2018-01-09

申请号：US15040814

申请日：2016-02-10

Applicant: Xilinx, Inc.

Inventor： Pradip K. Jha ,  Atul Srinivasan ,  Steven Banks ,  Nicholas A. Mezei

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077

Abstract: Methods and systems are disclosed for placement and routing of a circuit design. A set of timing constraints is retrieved that specifies timing for objects included in a first shell circuit design configured to provide an interface for communication between the circuit design and the set of dedicated hardware resources on an IC. One or more objects of the first shell circuit design that do not affect timing of the circuit design are identified and removed from the first shell circuit design to produce a second shell circuit design. The circuit design is placed and routed according to timing constraints specified for objects of the first shell circuit design that are included in the second shell circuit design. The placed and routed circuit design is stored in a memory circuit.

公开(公告)号：US10796058B1

公开(公告)日：2020-10-06

申请号：US16141723

申请日：2018-09-25

Applicant: Xilinx, Inc.

Inventor： Nicholas A. Mezei ,  Steven Banks ,  Meiwei Wu ,  Raymond Kong

IPC: G06F30/392 ,  G06F30/394 ,  G06F30/3312

Abstract: A platform design including a module black-box instance is loaded into computer hardware. Using the computer hardware, synchronous boundary crossings between a static region and the module black-box instance of the platform design are identified and objects of the platform design included in the synchronous boundary crossings are marked. Using the computer hardware, unmarked objects are removed from the platform design to generate a shell circuit design. A custom circuit design is implemented based on the shell circuit design and timing constraints corresponding to objects remaining in the shell circuit design.