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    Striped direct memory access circuit
    1.
    发明授权
    Striped direct memory access circuit 有权

    公开(公告)号：US10474599B1

    公开(公告)日：2019-11-12

    申请号：US15421306

    申请日：2017-01-31

    Applicant: Xilinx, Inc.

    Inventor： Sundararajarao Mohan

    IPC: G06F13/28 ,  G06F12/1081 ,  G06F13/16

    Abstract: An apparatus can include a read data mover circuit adapted to fetch a portion of data for each of a plurality of read channels. The read data mover circuit is adapted to output, to an accelerator circuit, a plurality of bits of data for each of the plurality of read channels concurrently as first streamed data. The apparatus can include a controller configured to control operation of the read data mover circuit. In another aspect, the apparatus can include a write data mover circuit adapted to receive second streamed data from the accelerator circuit and output the second streamed data in a different format. The controller may be configured to control operation of the write data mover circuit.

    MIGRATING ACCELERATORS BETWEEN COMPUTE SYSTEMS
    2.
    发明申请
    MIGRATING ACCELERATORS BETWEEN COMPUTE SYSTEMS 审中-公开

    公开(公告)号：US20180232254A1

    公开(公告)日：2018-08-16

    申请号：US15430231

    申请日：2017-02-10

    Applicant: Xilinx, Inc.

    Inventor： Sundararajarao Mohan

    IPC: G06F9/48 ,  G06F3/06 ,  G06F12/10 ,  G06F13/40

    Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.

    Migrating virtual machines between compute systems by transmitting programmable logic accelerator state
    4.
    发明授权
    Migrating virtual machines between compute systems by transmitting programmable logic accelerator state 有权

    公开(公告)号：US10740146B2

    公开(公告)日：2020-08-11

    申请号：US15430231

    申请日：2017-02-10

    Applicant: Xilinx, Inc.

    Inventor： Sundararajarao Mohan

    IPC: G06F9/48 ,  G06F3/06 ,  G06F12/10 ,  G06F13/30 ,  G06F9/50 ,  G06F9/46 ,  G06F13/40

    Abstract: Embodiments herein describe techniques for executing VMs on hosts that include an accelerator. The hosts can use the accelerators to perform specialized tasks such as floating-point arithmetic, encryption, image processing, etc. Moreover, VMs can be migrated between hosts. To do so, the state of the processor is saved on the current host thereby saving the state of the VM. For example, by saving the processor state, once the data corresponding to the VM is loaded into a destination host, the processor can be initialized to the saved state in order to resume the VM. In addition to saving the processor state, the embodiments herein save the state of the accelerator on a FPGA. That is, unlike previous systems where tasks executed by the accelerator are discarded when migrating the VM, the state of the accelerator can be saved and used to initialize an FPGA accelerator in the destination host.

    Hardware and software cosynthesis performance estimation
    6.
    发明授权
    Hardware and software cosynthesis performance estimation 有权
    硬件和软件合成性能估算

    公开(公告)号：US09147024B1

    公开(公告)日：2015-09-29

    申请号：US14535258

    申请日：2014-11-06

    Applicant: Xilinx, Inc.

    Inventor： Vinod K. Kathail ,  Hua Sun ,  Sundararajarao Mohan ,  L. James Hwang ,  Yogesh L. Chobe

    IPC: G06F17/50

    CPC classification number: G06F17/505 ,  G06F17/5045

    Abstract: Hardware and software co-synthesis performance estimation includes, for a design specified in a high level programming language and having a processor executable partition and a partition selected for hardware acceleration, estimating hardware latency for a hardware accelerator implementation of the selected partition, scheduling the selected partition using the hardware latency generating hardware partition latency information, and compiling an instrumented version of the design using a processor. The instrumented and compiled version of the design is executed generating software latency information. A design performance for the design is determined through combining the hardware partition latency information with the software latency information.

    Abstract translation: 硬件和软件协同合成性能估计包括对于以高级编程语言指定的设计并具有处理器可执行分区和为硬件加速选择的分区，估计所选分区的硬件加速器实现的硬件延迟，调度所选择的 分区，使用硬件延迟生成硬件分区延迟信息，并使用处理器编译设计版本的设计。 设计的仪器化和编译版本执行生成软件延迟信息。 通过将硬件分区延迟信息与软件延迟信息相结合来确定设计的设计性能。

    Blockchain machine network acceleration engine
    7.
    发明授权
    Blockchain machine network acceleration engine 有权

    公开(公告)号：US11657040B2

    公开(公告)日：2023-05-23

    申请号：US17084942

    申请日：2020-10-30

    Applicant: XILINX, INC.

    Inventor： Ji Yang ,  Haris Javaid ,  Sundararajarao Mohan ,  Gordon John Brebner

    IPC: G06F16/23 ,  G06F12/0875

    CPC classification number: G06F16/2379 ,  G06F12/0875 ,  G06F2212/45

    Abstract: Embodiments herein describe a hardware accelerator (e.g., a network acceleration engine) for a blockchain machine or node. The hardware accelerator parses packets containing separate components of a block of transactions to generate data to perform a validation process. To avoid the latency that comes with using software, the embodiments herein describe a protocol processor in the hardware accelerator that parses the packets and prepares the data so it can be consumed by downstream components in the accelerator without software intervention. These downstream components can then perform a validation operation to validate one or more transactions before those transactions are committed (i.e., added) to a ledger of a permissioned blockchain.

    Integration of a programmable device and a processing system in an integrated circuit package
    8.
    发明授权
    Integration of a programmable device and a processing system in an integrated circuit package 有权

    公开(公告)号：US11024583B2

    公开(公告)日：2021-06-01

    申请号：US16773501

    申请日：2020-01-27

    Applicant: XILINX, INC.

    Inventor： Austin H. Lesea ,  Sundararajarao Mohan ,  Stephen M. Trimberger

    IPC: G06F15/78 ,  H01L23/538 ,  H01L23/50

    Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

    Compilation of system designs
    9.
    发明授权
    Compilation of system designs 有权

    公开(公告)号：US09805152B1

    公开(公告)日：2017-10-31

    申请号：US15046147

    申请日：2016-02-17

    Applicant: Xilinx, Inc.

    Inventor： Jorge E. Carrillo ,  Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Hua Sun

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: In an example implementation, a method is provided for compiling an HLL source file including function calls to one or more hardware accelerated functions. Function calls in the HLL source file to hardware accelerated functions are identified and grouped into a plurality of subsets for exclusive implementation in programmable logic resources. Sets of configuration data are generated for configuration of the programmable logic resources to implement hardware accelerated functions for the respective subsets of function calls. An interface manager is generated and the identified function calls are replaced with interface code configured to communicate with the interface manager. The interface manager manages configuration of the programmable logic resources to switch between the sets of configuration data to implement hardware accelerated functions for different ones of the subsets.

    Automatic implementation of a customized system-on-chip
    10.
    发明授权
    Automatic implementation of a customized system-on-chip 有权

    公开(公告)号：US09652570B1

    公开(公告)日：2017-05-16

    申请号：US14845100

    申请日：2015-09-03

    Applicant: Xilinx, Inc.

    Inventor： Vinod K. Kathail ,  L. James Hwang ,  Sundararajarao Mohan ,  Jorge E. Carrillo ,  Hua Sun ,  Tom Shui ,  Yogesh L. Chobe

    IPC: G06F17/50

    CPC classification number: G06F17/505

    Abstract: Implementing a system-on-chip (SOC) design specified as a high level programming language (HLL) application may include querying, using a computer, a platform description to determine an available interface of a platform for a target integrated circuit and generating, using the computer, hardware for a function of the HLL application marked for hardware acceleration and hardware coupling the marked function with the available interface of the platform. Implementing the SOC design may also include modifying, using the computer, the HLL application with program code configured to access the generated hardware for the marked function and building, using the computer, the hardware and the software of the SOC design.

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