公开(公告)号：US09530022B1

公开(公告)日：2016-12-27

申请号：US14502996

申请日：2014-09-30

Applicant: Xilinx, Inc.

Inventor： Jason J. Moore ,  James B. Anderson ,  James D. Wesselkamper ,  Stephen M. Trimberger

IPC: G06F21/44 ,  G06F21/62 ,  G06F9/445

CPC classification number: G06F8/61 ,  G06F21/75

Abstract: In one approach for protecting a design, a plurality of implementations of the design are generated. Each implementation includes an identification function. One of the implementations is selected as a current implementation, and the current implementation is installed on one or more electronic systems. For each electronic system, a method determines whether or not the current implementation is an authorized version on the electronic system from an output value of the identification function. If in the current implementation is not an authorized version on the electronic system, a signal is output indicating that the current implementation is not an authorized version on the electronic system. Periodically, another one of the implementations is selected as a new current implementation, and the new current installation is used for installations on one or more electronic systems.

Abstract translation: 在保护设计的一种方法中，生成设计的多个实现。 每个实现包括识别功能。 选择其中一个实现作为当前实现，并且当前实现被安装在一个或多个电子系统上。 对于每个电子系统，一种方法从识别功能的输出值确定当前实现是否是电子系统上的授权版本。 如果在当前实现中不是电子系统上的授权版本，则输出指示当前实现不是电子系统上的授权版本的信号。 周期性地，另外一个实现被选择为新的当前实现，并且新的当前安装被用于一个或多个电子系统上的安装。

公开(公告)号：US10860044B1

公开(公告)日：2020-12-08

申请号：US15377583

申请日：2016-12-13

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: G05F1/46 ,  G05F1/575

Abstract: Apparatuses and methods relating generally to reduction of allocation of external power and/or ground pins of a microelectronic device are disclosed. In one such apparatus, an external power input pin is configured for receiving an input supply-side power having an external supply voltage level higher than an internal supply voltage level and an external supply current level lower than an internal supply current level. An internal power plane circuit coupled to the external power input pin is configured to step-down a voltage from the external supply voltage level to the internal supply voltage level and to step-up a current from the external supply current level to the internal supply current level to provide an internal power source.

公开(公告)号：US10657292B2

公开(公告)日：2020-05-19

申请号：US15845958

申请日：2017-12-18

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: G06F17/50 ,  G06F21/76 ,  G06F15/78

Abstract: An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.

公开(公告)号：US10573598B2

公开(公告)日：2020-02-25

申请号：US15719288

申请日：2017-09-28

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Sundararajarao Mohan ,  Stephen M. Trimberger

IPC: G06F15/78 ,  H01L23/538 ,  H01L23/50

Abstract: An example integrated circuit (IC) package includes: a processing system and a programmable IC disposed on a substrate, the processing system coupled to the programmable IC through interconnect of the substrate; the processing system including components coupled to a ring interconnect, the components including a processor and an interface controller. The programmable IC includes: an interface endpoint coupled to the interface controller through the interconnect; and at least one peripheral coupled to the interface endpoint and configured for communication with the ring interconnect of the processing system through the interconnect endpoint and the interface controller.

公开(公告)号：US10536477B1

公开(公告)日：2020-01-14

申请号：US15343539

申请日：2016-11-04

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: H04L29/06

Abstract: Disclosed approaches for protecting against attacks on a local network device include establishing an access period associated with one remote network device of a plurality of remote network devices. The router rejects messages from remote network devices of the plurality of remote network devices not having associated access periods. The router forwards to the local network device, a message received from the one remote network device during the access period. The router rejects, in response to expiration of the access period, subsequent messages from the one remote network device to the local network device.

公开(公告)号：US10476598B1

公开(公告)日：2019-11-12

申请号：US15219005

申请日：2016-07-25

Applicant: Xilinx, Inc.

Inventor： Austin H. Lesea ,  Stephen M. Trimberger

IPC: H01L25/00 ,  H04B10/50 ,  H04B10/508

Abstract: Various apparatuses, circuits, systems, and methods for optical communication are disclosed. In some implementations, an apparatus includes a package substrate and f first interposer mounted on the package substrate. The apparatus also includes a logic circuit and an optical interface circuit connected to the logic circuit via the first interposer. One of the optical interface circuit or the logic circuit is mounted on the first interposer. The optical interface circuit includes a driver circuit configured to receive electronic data signals from the logic circuit. The optical interface circuit also includes an optical transmitter circuit coupled to the driver circuit and configured to output optical data signals encoding the electronic data signals.

公开(公告)号：US20190188419A1

公开(公告)日：2019-06-20

申请号：US15845958

申请日：2017-12-18

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: G06F21/76

CPC classification number: G06F21/76 ,  G06F15/7867 ,  G06F17/5054

Abstract: An example method of configuring a programmable integrated circuit (IC) in a computer system includes: selecting a first region of a programmable fabric of the programmable IC for implementation of a shell circuit, the shell circuit configured to interface with a bus of the computer system; selecting a second region of the programmable fabric for implementation of an application circuit, the application circuit configured to interface with the shell circuit; providing a fence region disposed between the first region and the second region, the fence region including a set of un-configured tiles of the programmable fabric; generating configuration data for a circuit design having the first region, the second region, and the fence region; and loading the configuration data to the programmable IC.

公开(公告)号：US09444618B1

公开(公告)日：2016-09-13

申请号：US13867429

申请日：2013-04-22

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger ,  Austin H Lesea

IPC: H04L9/00 ,  H04L9/34

CPC classification number: H04L9/002 ,  H04L9/3278 ,  H04L9/34 ,  H04L2209/805

Abstract: Circuits and methods are disclosed for defending against attacks on ring oscillator-based physically unclonable functions (RO PUFs). A control circuit that is coupled to the RO PUF is configured to detect out-of-tolerance operation of the RO PUF. In response to detecting out-of-tolerance operation of the RO PUF, the control circuit disables the RO PUF, and in response to detecting in-tolerance operation, the control circuit enables the RO PUF.

Abstract translation: 公开了电路和方法，以防止对基于环形振荡器的物理不可克隆功能（RO PUF）的攻击。 耦合到RO PUF的控制电路被配置为检测RO PUF的超出公差的操作。 响应于检测到RO PUF的超出公差的操作，控制电路禁用RO PUF，并且响应于检测到公差操作，控制电路使能RO PUF。

公开(公告)号：US09372956B1

公开(公告)日：2016-06-21

申请号：US14537295

申请日：2014-11-10

Applicant: Xilinx, Inc.

Inventor： Yuezhen Fan ,  Eric J. Thorne ,  Xiao-Yu Li ,  Glenn O'Rourke ,  Stephen M. Trimberger

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5054

Abstract: A method of enabling the use of a programmable device having impaired circuitry includes determining one or more locations of the impaired circuitry of the programmable device; generating a defect map for the programmable device based on the determined locations of the impaired circuitry; generating a plurality of configuration bitstreams to implement a circuit in the programmable device; selecting one of the plurality of configuration bitstreams that does not use the impaired circuitry indicated by the defect map; and programming the programmable device with the selected configuration bitstream.

Abstract translation: 能够使用具有受损电路的可编程设备的方法包括确定可编程设备的受损电路的一个或多个位置; 基于所确定的受损电路的位置，生成可编程设备的缺陷图; 生成多个配置比特流以实现可编程设备中的电路; 选择不使用由缺陷图指示的受损电路的多个配置比特流中的一个; 以及使用所选择的配置比特流对可编程设备进行编程。

公开(公告)号：US10325646B1

公开(公告)日：2019-06-18

申请号：US14854870

申请日：2015-09-15

Applicant: Xilinx, Inc.

Inventor： Stephen M. Trimberger

IPC: H04L29/06 ,  G11C11/413 ,  H03K19/177 ,  H03K19/003 ,  G06F21/75 ,  G06F21/76 ,  G11C5/14

Abstract: The disclosure describes approaches for generating a physically unclonable function (PUF) value. Power is applied to a power control circuit, an SRAM, and a PUF control circuit. After initially powering-up the SRAM, the PUF control circuit signals the power control circuit to disable power to the SRAM. The power control circuit disables power to the SRAM, and then re-enables power to the SRAM after having power to the SRAM disabled for a waiting period. The PUF control circuit reads a PUF value from the SRAM by the PUF control circuit after the enabling of power.