公开(公告)号：US10275259B1

公开(公告)日：2019-04-30

申请号：US15008062

申请日：2016-01-27

Applicant: Xilinx, Inc.

Inventor： Sunita Jain

IPC: G06F9/445 ,  G06F9/4401

Abstract: Methods and systems are disclosed for booting an integrated circuit (IC). In an example implementation, boot read only memory (ROM) code is loaded for execution by a processor circuit of the IC. Via execution of the boot ROM code on the processor circuit, a first boot image is retrieved. A memory address is communicated from a host device to the processor circuit of the IC via an external data bus coupled to a bus interface circuit in the IC. The bus interface circuit is configured by execution of the first boot image to map a first block of addresses on the internal data bus to a second block of addresses on the host device starting at the memory address. When bus mastering is enabled, the processor retrieves a second boot image from the host device by issuing read requests to the first block of addresses.

公开(公告)号：US11734217B2

公开(公告)日：2023-08-22

申请号：US17644068

申请日：2021-12-13

Applicant: XILINX, INC.

Inventor： Sunita Jain ,  Bharat Kumar Gogada ,  Arjun Vynipadath ,  Meera Bagdai

IPC: G06F13/42 ,  G06F13/40

CPC classification number: G06F13/4221 ,  G06F13/4063 ,  G06F2213/0026

Abstract: Embodiments herein describe using software or firmware to manage the device capability list of a PCIe device. That is, rather than relying on pure hardware to advertise the capabilities of a PCIe device, the embodiments herein permit software or firmware executing on a processor in the PCIe device to manage read and write requests associated with discovering the capabilities of the device and configuring the device.

公开(公告)号：US10783103B1

公开(公告)日：2020-09-22

申请号：US15442528

申请日：2017-02-24

Applicant: Xilinx, Inc.

Inventor： Sunita Jain ,  Bharat Kumar Gogada ,  Ravikiran Gummaluri

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/42 ,  G06F13/38

Abstract: A signature is generated to indicate a direct memory access (DMA) operation involving a transfer, by a DMA engine, of data between a host memory circuit and an endpoint memory circuit of an endpoint processor circuit. First descriptors of the DMA engine are defined relative to the endpoint memory circuit or host memory circuit. A signature is received that indicates that second descriptors have been configured by the endpoint processor circuit. In response to receiving the endpoint signature, the DMA engine is enabled to begin the DMA operation.

公开(公告)号：US10719464B1

公开(公告)日：2020-07-21

申请号：US16401104

申请日：2019-05-01

Applicant: Xilinx, Inc.

Inventor： Sunita Jain ,  Sweatha Rao

IPC: G06F13/362

Abstract: An example hardware accelerator in a computing system includes a bus interface coupled to a peripheral bus of the computing system; a lock circuit coupled to the bus interface; and a plurality of kernel circuits coupled to the lock circuit and the bus interface; wherein the plurality of kernel circuits provide lock requests to the lock circuit, the lock requests for data stored in system memory of the computing system; wherein the lock circuit is configured to process the lock requests from the plurality of kernel circuits and to issue atomic transactions over the peripheral bus through the bus interface based on the lock requests.

公开(公告)号：US09965417B1

公开(公告)日：2018-05-08

申请号：US14995124

申请日：2016-01-13

Applicant: Xilinx, Inc.

Inventor： Sarosh I. Azad ,  Sunita Jain

IPC: G06F13/32 ,  G06F13/16 ,  G06F13/42 ,  G06F12/1081

CPC classification number: G06F13/32 ,  G06F12/1081 ,  G06F13/1642 ,  G06F13/4282 ,  G06F2212/656

Abstract: Techniques for communication with a host system via a peripheral component interconnect express (PCIe) communication fabric are disclosed herein. A peripheral device having its own memory address space executes a boot ROM to initialize a PCIe-to internal memory address space bridge and to disable MSIx interrupts. The peripheral device monitors a specific location in memory dedicated to MSIx interrupts for a particular value that indicates that PCIe device enumeration is complete. At this point, the peripheral device knows that its PCIe base address registers have been set by the host, and sets address translation registers for translating addresses in the address space of the host to the address space of the peripheral device.