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    Data processor for processing a complex instruction by dividing it into executing units
    6.
    发明授权
    Data processor for processing a complex instruction by dividing it into executing units 失效
    数据处理器，用于通过将复杂指令分为执行单元来处理

    公开(公告)号：US6092183A

    公开(公告)日：2000-07-18

    申请号：US401691

    申请日：1995-03-10

    申请人： Hidehito Takewa ,  Shigeru Matsuo ,  Shinji Fujiwara ,  Masahisa Narita

    发明人： Hidehito Takewa ,  Shigeru Matsuo ,  Shinji Fujiwara ,  Masahisa Narita

    IPC分类号： G06F9/30 ,  G06F9/38

    CPC分类号： G06F9/3802 ,  G06F9/30101 ,  G06F9/30145 ,  G06F9/3861 ,  G06F9/3867

    摘要： A compact and small compensating-electric-power data processor is realized by dividing a plurality of calculations to be carried out by a complex instruction into a number of executing units to be processed, instead of executing the calculations in parallel as in the past. For this purpose there is provided a decoder having a detecting part for decoding an instruction and for detecting whether the instruction is an instruction for executing a plurality of calculations, a field rearranging part for rearranging a part of the fields of said instruction based on a predetermined number of calculations to be processed if it is judged by said detecting part that the instruction is an instruction for executing a plurality of calculations, and a calculation control part for performing control to execute the calculations in plural cycles in synchronism with the order of said rearranged fields. A calculation part operates to execute the calculations called for by dividing the instruction into plural cycles based on control from the calculation control part.

    摘要翻译： 通过将要由复杂指令执行的多个计算划分成要处理的多个执行单元来实现紧凑而小的补偿电力数据处理器，而不是如以前那样并行地执行计算。 为此，提供了一种解码器，具有用于对指令进行解码并检测该指令是否是用于执行多个计算的指令的检测部分，用于基于预定的方式重排所述指令的一部分字段的字段重排部分 如果由所述检测部分判断所述指令是用于执行多个计算的指令，则要处理的计算次数以及用于执行控制以与所述重新排列的顺序同步地执行多个周期的计算的计算控制部分 领域。 计算部分通过根据来自计算控制部分的控制将指令分成多个周期来进行所需的计算。

    Arithmetic unit capable of performing concurrent operations for high speed operation
    7.
    发明授权
    Arithmetic unit capable of performing concurrent operations for high speed operation 失效
    算术单元能够执行高速运行的并发操作

    公开(公告)号：US5623435A

    公开(公告)日：1997-04-22

    申请号：US371998

    申请日：1995-01-12

    申请人： Hidehito Takewa ,  Hiromichi Yamada ,  Takashi Hotta ,  Kotaro Shimamura

    发明人： Hidehito Takewa ,  Hiromichi Yamada ,  Takashi Hotta ,  Kotaro Shimamura

    IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537 ,  G06F7/57

    CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/485 ,  G06F7/5375 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957

    摘要： An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values; has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.

    摘要翻译： 一个算术单元，接受两个数值，并通过使用两个数值执行一个操作; 具有用于基于从接受的两个数值直接或间接获得的两个数值来执行加法或减法的加法器 - 减法器; 用于执行归一化处理的归一化器，其中相加或相减结果的尾数部分被移位，使得在结果中重新显现的高阶数字可以到达预定位置，并且其中结果的指数部分 根据尾数部分的偏移位置的数量进行校正; 以及用于执行舍入处理的舍入装置，其中，在相加或相减结果的尾数部分超过预定数量的数字的条件下，尾数部分的位数根据预先指定的舍入模式而减少。 舍入装置与加法器 - 减法器或归一化器的执行并行，通过使用尚未进行归一化处理的数值来执行舍入处理的至少一部分。

    Arithmetic unit capable of performing concurrent operations for high speed operation
    9.
    发明授权
    Arithmetic unit capable of performing concurrent operations for high speed operation 失效
    算术单元能够执行高速运行的并发操作

    公开(公告)号：US5408426A

    公开(公告)日：1995-04-18

    申请号：US037654

    申请日：1993-03-17

    申请人： Hidehito Takewa ,  Hiromichi Yamada ,  Takashi Hotta ,  Kotaro Shimamura

    发明人： Hidehito Takewa ,  Hiromichi Yamada ,  Takashi Hotta ,  Kotaro Shimamura

    IPC分类号： G06F7/50 ,  G06F7/52 ,  G06F7/535 ,  G06F7/537 ,  G06F7/57 ,  G06F7/38

    CPC分类号： G06F7/535 ,  G06F7/483 ,  G06F7/485 ,  G06F7/5375 ,  G06F7/4873 ,  G06F7/49936 ,  G06F7/49957

    摘要： An arithmetic unit which accepts two numerical values and executes an operation by the use of the two numerical values has an adder-subtracter for executing an addition or a subtraction on the basis of two numerical values obtained directly or indirectly from the accepted two numerical values; a normalizer for executing a normalizing process in which a mantissa part of an added or subtracted result is shifted so that a high-order digit having been developed anew in the result may come to a predetermined position, and in which an exponent part of the result is corrected in accordance with the number of shift places in the shift of the mantissa part; and a rounding device for executing a rounding process in which, on condition that the mantissa part of the added or subtracted result exceeds a predetermined number of digits, the number of digits of the mantissa part is reduced in conformity with a rounding mode designated beforehand. The rounding device executes at least part of the rounding process by the use of the numerical values not yet subjected to the normalizing process, in parallel with the execution of the adder-subtracter or the normalizer.

    摘要翻译： 接受两个数值并通过使用两个数值执行操作的算术单元具有加法器 - 减法器，用于基于从接受的两个数值直接或间接获得的两个数值来执行加法或减法运算; 用于执行归一化处理的归一化器，其中相加或相减结果的尾数部分被移位，使得在结果中重新显现的高阶数字可以到达预定位置，并且其中结果的指数部分 根据尾数部分的偏移位置的数量进行校正; 以及用于执行舍入处理的舍入装置，其中，在相加或相减结果的尾数部分超过预定数量的数字的条件下，尾数部分的位数根据预先指定的舍入模式而减少。 舍入装置与加法器 - 减法器或归一化器的执行并行，通过使用尚未进行归一化处理的数值来执行舍入处理的至少一部分。