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公开(公告)号：US09367438B2
公开(公告)日：2016-06-14
申请号：US14110786
申请日：2011-04-21
CPC分类号： G06F12/02 , G06F11/1641 , G06F11/167 , G06F11/1687 , G06F2201/845
摘要： First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.
摘要翻译： 从功能模块（2）输出的要写入的第一数据被提供给内置存储器（3）和第一缓冲存储器（11），以及从功能模块（2）输出的要写入的第二数据 ）被提供给内置存储器（3）和第二缓冲存储器（12）。 第一和第二FIFO存储器（13,14）从从第一和第二缓冲存储器（11,12）顺次输出的多个第一和第二输出数据项中选择并存储具有预定数量的输出的数据项，以及 不要选择其他数据项。 比较器（15）将由第一和第二FIFO存储器（13,14）输出的具有预定数量的输出的数据项彼此进行比较。
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公开(公告)号：US20130020978A1
公开(公告)日：2013-01-24
申请号：US13555123
申请日：2012-07-21
申请人： Hiromichi YAMADA , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
发明人： Hiromichi YAMADA , Teruaki Sakata , Nobuyasu Kanekawa , Yuichi Ishiguro , Takashi Yasumasu , Kazuyoshi Fukuda , Kesami Hagiwara
CPC分类号： G06F11/0754 , G06F11/0739 , G06F13/00 , Y02D10/14
摘要： A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.
摘要翻译： 微控制器包括中央处理单元，根据由中央处理单元设置的PWM信号的生成条件产生PWM信号的PWM信号生成单元，以及在其中输入生成的PWM信号并检测脉冲周期的诊断单元 以及基于输入信号的脉冲宽度，并且确定检测到的脉冲周期和脉冲宽度是否与脉冲周期和对应于生成条件的脉冲宽度一致。
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公开(公告)号：US08046137B2
公开(公告)日：2011-10-25
申请号：US13004414
申请日：2011-01-11
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
摘要翻译： 提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作 利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。 触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟 根据其输入信号。
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公开(公告)号：US20110106335A1
公开(公告)日：2011-05-05
申请号：US13004414
申请日：2011-01-11
CPC分类号： G06F11/1641 , G06F11/1679 , Y02T10/82
摘要： Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.
摘要翻译： 提供具有相同功能的两个数据处理单元，其中一个用于主机，另一个用于比较，电机单元的控制由主机执行，主数据处理单元和电路单元同步操作 利用第一时钟信号，第二数据处理单元与具有与第一时钟信号相同的周期和不同相位的第二时钟信号同步地操作，并且在比较电路中比较两个数据处理单元的处理结果。 触发器设置在从电路单元到比较数据处理单元和从主数据处理单元到比较器的信号路径的信号路径上，并且第一和第二时钟信号都用于触发器的锁存时钟 根据其输入信号。
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公开(公告)号：US20100251017A1
公开(公告)日：2010-09-30
申请号：US12721208
申请日：2010-03-10
CPC分类号： G06F11/1048 , G06F11/0724 , G06F11/0772 , G06F12/0811
摘要： The data processor having CPUs each capable of accessing memories enables the processing of a memory error according to the processing mode of the data processor. The CPUs have a memory, and each include a first storing unit capable of storing CPU-identifying information which enables identification of CPU having accessed the memory. At the time of occurrence of a soft error owing to access to the memory, the CPU, having the memory, stores the CPU-identifying information for identifying the CPU having accessed the corresponding memory in the first storing unit, and notifies the interrupt controller of occurrence of a soft error of the memory. After having received an interruption of the memory soft error from the interrupt controller, the CPU uses information stored in the first storing unit to identify the CPU having made the access, and performs the error processing.
摘要翻译： 具有能够访问存储器的CPU的数据处理器能够根据数据处理器的处理模式来处理存储器错误。 CPU具有存储器，并且每个都包括能够存储CPU识别信息的第一存储单元，其能够识别已访问存储器的CPU。 在由于访问存储器而发生软错误时，具有存储器的CPU存储用于识别在第一存储单元中访问相应存储器的CPU的CPU识别信息，并将中断控制器通知 发生内存的软错误。 在从中断控制器接收到存储器软错误的中断之后，CPU使用存储在第一存储单元中的信息来识别已经进行访问的CPU，并且执行错误处理。
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公开(公告)号：US20100217943A1
公开(公告)日：2010-08-26
申请号：US12706938
申请日：2010-02-17
IPC分类号： G06F12/00
CPC分类号： G06F11/1641 , G06F11/1683
摘要： A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.
摘要翻译： 其中相应CPU执行不同应用以提高处理性能的微控制器，并且相应的CPU执行需要安全性并相互比较其结果的应用，以提供写入数据的可靠性。 微控制器具有由第一CPU，第二CPU，第一存储器和第二存储器构成的多个处理系统，并且对于关于预先设定的特定处理的指令处理，执行未复用的对外围模块的写入 两次，并且第一次和第二次的写入数据被相互整理。
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公开(公告)号：US20060274939A1
公开(公告)日：2006-12-07
申请号：US11447434
申请日：2006-06-06
申请人： Hiromichi Yamada
发明人： Hiromichi Yamada
IPC分类号： G06K9/34
CPC分类号： H04N1/00867 , G03G21/04 , H04N1/0087 , H04N2201/0098
摘要： A copy-forgery-inhibited (CFI) pattern image is effectively printed irrespective of difference in information of (CFI) pattern setting between a host unit and a printing apparatus in relation to printing of a (CFI) pattern image. A (CFI) pattern image, for example, “COPY INHIBIT” is set on the printer side while a (CFI) pattern image “COPY” is set under a printing instruction delivered from a host PC. If determination is resulted in inconsistency between strings, indication for asking the user which (CFI) pattern image is given preference to be displayed on an UI screen of the printer. Further, similar indication is displayed on the host PC side. Thus, it is possible to render the user to determine whether the setting of a (CFI) pattern image on the host PC side is given preference to or the setting on the printer side is given preference to.
摘要翻译： 与CFI图案图像的打印相关的主机单元和打印装置之间的（CFI）图案设置的信息差异无论打印有效地打印禁止复制伪造图案（CFI）图案图像。 在（CFI）图案图像“COPY”被设置在从主PC发送的打印指令的情况下，在打印机侧设置例如“COPY INHIBIT”的（CFI）图案图像。 如果确定字符串之间不一致，则向用户询问哪个（CFI）图案图像被优先显示在打印机的UI屏幕上的指示。 此外，在主机侧显示类似的指示。 因此，可以使用户确定主机PC侧的（CFI）图案图像的设置是否优先于打印机侧的设置，或者优先于打印机侧的设置。
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公开(公告)号：US06986029B2
公开(公告)日：2006-01-10
申请号：US10201249
申请日：2002-07-24
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
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9.发明申请Micro-controller for reading out compressed instruction code and program memory for compressing instruction code and storing therein 审中-公开用于读出压缩指令代码的微控制器和用于压缩指令代码并存储在其中的程序存储器公开(公告)号：US20050198471A1
公开(公告)日：2005-09-08
申请号：US11117509
申请日：2005-04-29
申请人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
发明人： Hiromichi Yamada , Dai Fujii , Yasuhiro Nakatsuka , Takashi Hotta , Kotaro Shimamura , Tatsuki Inuduka , Takanaga Yamazaki
CPC分类号： G06F9/30178 , Y10S707/99942
摘要： A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.
摘要翻译： 微控制器包括用于存储出现在程序中的指令代码的字典存储器和用于存储从程序中包括的每个指令代码转换的压缩代码的压缩代码存储器。 每个压缩代码的字长足够长以识别程序中包含的所有指令代码。 每个压缩代码具有指示存储相关联的指令代码的字典存储器中的地址的值。 微控制器响应于指定代码读取请求，其指定压缩代码的地址以读取存储在压缩代码存储器中的指定地址中的压缩代码，并且随后读取存储在由压缩代码存储器指示的地址中的指令代码 字典内存中的压缩代码。
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公开(公告)号：US20050091428A1
公开(公告)日：2005-04-28
申请号：US10491285
申请日：2001-10-02
摘要： A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer. A serial data transferring apparatus is realized which can simplify the structure of the slave unit, cut the total cost, and reduce noise.
摘要翻译： 主单元向从单元发送启动信号。 当从主单元接收到起始信号时，从单元向主单元发送同步字段，该同步字段是指示从单元能够执行传送和接收操作的传送时钟的数据串（脉冲信号） 。 主单元根据从从单元发送的同步字段指示的传送时钟向从属单元发送命令数据。 响应于从主单元发送的命令数据，从单元根据由同步字段指示的传送时钟向主单元发送响应数据。 因此，在采用本发明的串行数据传送装置的通信系统中，主单元建立用于数据传送的同步，而从单元没有建立用于数据传送的同步的负担。 实现了串行数据传送装置，其可以简化从单元的结构，降低总成本并降低噪声。
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