公开(公告)号：US20180211910A1

公开(公告)日：2018-07-26

申请号：US15809373

申请日：2017-11-10

Applicant: Yongkyu LEE ,  Gwanhyeob Koh ,  Boyoung Seo

Inventor： Yongkyu LEE ,  Gwanhyeob Koh ,  Boyoung Seo

IPC: H01L23/528 ,  H01L27/22 ,  H01L43/08

CPC classification number: H01L23/528 ,  H01L27/222 ,  H01L27/2481 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08

Abstract: A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.

公开(公告)号：US20170110653A1

公开(公告)日：2017-04-20

申请号：US15294100

申请日：2016-10-14

Applicant: Boyoung SEO ,  Seongui SEO ,  Gwanhyeob KOH ,  Yongkyu LEE

Inventor： Boyoung SEO ,  Seongui SEO ,  Gwanhyeob KOH ,  Yongkyu LEE

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

CPC classification number: G11C11/165 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

Abstract: A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

公开(公告)号：US20170110171A1

公开(公告)日：2017-04-20

申请号：US15293782

申请日：2016-10-14

Applicant: BOYOUNG SEO ,  Yongkyu LEE ,  Gwanhyeob KOH ,  Cheong Jae LEE

Inventor： BOYOUNG SEO ,  Yongkyu LEE ,  Gwanhyeob KOH ,  Cheong Jae LEE

IPC: G11C11/16 ,  H01L27/112 ,  G11C17/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

CPC classification number: G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

Abstract: A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.