公开(公告)号：US10311928B2

公开(公告)日：2019-06-04

申请号：US15293782

申请日：2016-10-14

申请人： Boyoung Seo ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

发明人： Boyoung Seo ,  Yongkyu Lee ,  Gwanhyeob Koh ,  Choong Jae Lee

IPC分类号： G11C11/00 ,  G11C17/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/08 ,  H01L43/10

摘要： A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.

公开(公告)号：US10269401B2

公开(公告)日：2019-04-23

申请号：US15294100

申请日：2016-10-14

申请人： Boyoung Seo ,  Seongui Seo ,  Gwanhyeob Koh ,  Yongkyu Lee

发明人： Boyoung Seo ,  Seongui Seo ,  Gwanhyeob Koh ,  Yongkyu Lee

IPC分类号： G11C11/16 ,  H01L27/22

摘要： A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

公开(公告)号：US20180211910A1

公开(公告)日：2018-07-26

申请号：US15809373

申请日：2017-11-10

申请人： Yongkyu LEE ,  Gwanhyeob Koh ,  Boyoung Seo

发明人： Yongkyu LEE ,  Gwanhyeob Koh ,  Boyoung Seo

IPC分类号： H01L23/528 ,  H01L27/22 ,  H01L43/08

CPC分类号： H01L23/528 ,  H01L27/222 ,  H01L27/2481 ,  H01L43/08 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08

摘要： A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.

公开(公告)号：US10256190B2

公开(公告)日：2019-04-09

申请号：US15809373

申请日：2017-11-10

申请人： Yongkyu Lee ,  Gwanhyeob Koh ,  Boyoung Seo

发明人： Yongkyu Lee ,  Gwanhyeob Koh ,  Boyoung Seo

IPC分类号： H01L23/528 ,  H01L43/08 ,  H01L27/22 ,  H01L45/00 ,  H01L27/24

摘要： A variable resistance memory device includes different variable resistance patterns on different memory regions of a substrate. The different variable resistance patterns may be at different heights from the substrate and may have different intrinsic properties. The different variable resistance patterns may at least partially comprise separate memory cells that are each configured to function as a non-volatile memory cell or a random access memory cell, respectively.

公开(公告)号：US20150131387A1

公开(公告)日：2015-05-14

申请号：US14508043

申请日：2014-10-07

申请人： ChangMin Jeon ,  Teakwang YU ,  Yongtae KIM ,  Boyoung SEO

发明人： ChangMin Jeon ,  Teakwang YU ,  Yongtae KIM ,  Boyoung SEO

IPC分类号： G11C16/14 ,  G11C16/08

CPC分类号： G11C16/08 ,  G11C16/06 ,  G11C16/16

摘要： A logic embedded nonvolatile memory device is provided which includes a first erase gate line for erasing a plurality of first memory cells; a second erase gate line electrically separated from the first erase gate line and for erasing a plurality of second memory cells; a global erase gate line supplied with an erase voltage; and an erase gate selection switch formed between the first memory cells and the second memory cells, wherein the erase gate selection switch connects the global erase gate line to the first erase gate line or the second erase gate line according to an erase control signal.

摘要翻译： 提供了一种逻辑嵌入式非易失性存储器件，其包括用于擦除多个第一存储器单元的第一擦除栅线; 与第一擦除栅极线电分离并用于擦除多个第二存储器单元的第二擦除栅极线; 提供有擦除电压的全局擦除栅极线; 以及形成在第一存储单元和第二存储单元之间的擦除栅极选择开关，其中擦除栅极选择开关根据擦除控制信号将全局擦除栅极线连接到第一擦除栅极线或第二擦除栅极线。

公开(公告)号：US20130197703A1

公开(公告)日：2013-08-01

申请号：US13806583

申请日：2011-06-27

申请人： Junho Ahn ,  Yanghwan Kim ,  Hoonbong Lee ,  Koonseok Lee ,  Jinhwan Son ,  Boyoung Seo ,  Hansu Jung

发明人： Junho Ahn ,  Yanghwan Kim ,  Hoonbong Lee ,  Koonseok Lee ,  Jinhwan Son ,  Boyoung Seo ,  Hansu Jung

IPC分类号： G06F1/28

CPC分类号： G06F1/28 ,  H02J3/14 ,  H02J3/381 ,  H02J3/46 ,  Y02B70/3225 ,  Y04S20/222

摘要： Provided is a component for a network system.

摘要翻译： 提供了一种网络系统的组件。

公开(公告)号：US20180122467A1

公开(公告)日：2018-05-03

申请号：US15663416

申请日：2017-07-28

申请人： SUK-SOO PYO ,  HYUNTAEK JUNG ,  TAEJOONG SONG ,  BOYOUNG SEO

发明人： SUK-SOO PYO ,  HYUNTAEK JUNG ,  TAEJOONG SONG ,  BOYOUNG SEO

IPC分类号： G11C13/00

CPC分类号： G11C13/0064 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1677 ,  G11C11/1693 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/003 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0073 ,  G11C2213/74 ,  G11C2213/79 ,  G11C2213/82

摘要： An operating method of a nonvolatile memory device includes storing different data in first and second reference cells connected to a word line, checking whether the different data are abnormally stored in the first and second reference cells, and when it is determined that the different data are abnormally stored in the first and second reference cells, swapping the first and second reference cells.

公开(公告)号：US20180069175A1

公开(公告)日：2018-03-08

申请号：US15474388

申请日：2017-03-30

申请人： JUNGHOON BAK ,  Myoungsu SON ,  BOYOUNG SEO

发明人： JUNGHOON BAK ,  Myoungsu SON ,  BOYOUNG SEO

IPC分类号： H01L43/12 ,  H01L43/08

CPC分类号： H01L43/12 ,  G11C11/15 ,  G11C11/5607 ,  G11C14/0036 ,  G11C19/02 ,  G11C2211/5615 ,  H01L27/222 ,  H01L27/224 ,  H01L29/82 ,  H01L43/02 ,  H01L43/08

摘要： Disclosed is a method of fabricating a magnetic memory device. The method of a fabricating a magnetic memory device includes forming an interlayer dielectric layer on a substrate, forming a sacrificial pattern in the interlayer dielectric layer, forming a magnetic tunnel junction pattern on the sacrificial pattern, after forming the magnetic tunnel junction pattern, selectively removing the sacrificial pattern to form a bottom contact region in the interlayer dielectric layer, and forming a bottom contact in the bottom contact region.

公开(公告)号：US20170110653A1

公开(公告)日：2017-04-20

申请号：US15294100

申请日：2016-10-14

申请人： Boyoung SEO ,  Seongui SEO ,  Gwanhyeob KOH ,  Yongkyu LEE

发明人： Boyoung SEO ,  Seongui SEO ,  Gwanhyeob KOH ,  Yongkyu LEE

IPC分类号： H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L27/22

CPC分类号： G11C11/165 ,  G11C11/161 ,  G11C11/1675 ,  H01L27/228

摘要： A magnetic memory device includes a substrate, a landing pad on the substrate, first and second magnetic tunnel junction patterns disposed on the interlayer insulating layer and spaced apart from the landing pad when viewed from a plan view, and an interconnection structure electrically connecting a top surface of the second magnetic tunnel junction pattern to the landing pad. A distance between the landing pad and the first magnetic tunnel junction pattern is greater than a distance between the first and second magnetic tunnel junction patterns, and a distance between the landing pad and the second magnetic tunnel junction pattern is greater than the distance between the first and second magnetic tunnel junction patterns, when viewed from a plan view.

公开(公告)号：US20170110171A1

公开(公告)日：2017-04-20

申请号：US15293782

申请日：2016-10-14

申请人： BOYOUNG SEO ,  Yongkyu LEE ,  Gwanhyeob KOH ,  Cheong Jae LEE

发明人： BOYOUNG SEO ,  Yongkyu LEE ,  Gwanhyeob KOH ,  Cheong Jae LEE

IPC分类号： G11C11/16 ,  H01L27/112 ,  G11C17/02 ,  H01L43/08 ,  H01L43/10 ,  H01L27/22 ,  H01L43/02

CPC分类号： G11C11/161 ,  G11C11/1673 ,  G11C11/1675 ,  G11C17/02 ,  H01L27/228 ,  H01L43/08 ,  H01L43/10

摘要： A semiconductor device includes a memory cell array, which further includes an array of first magnetic memory cells and an array of second magnetic memory cells. Each of the first magnetic memory cells includes a first magnetic tunnel junction structure having a reversible resistance state, and each of the second magnetic memory cells includes a second magnetic tunnel junction structure having a one-time programmable (OTP) resistance state.