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公开(公告)号：US20130198710A1
公开(公告)日：2013-08-01
申请号：US13362914
申请日：2012-01-31
申请人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
摘要翻译： 提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。 该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。 设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。 可以从特定设备区域到周围区域监视梯度。 用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。
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公开(公告)号：US08549453B2
公开(公告)日：2013-10-01
申请号：US13362914
申请日：2012-01-31
申请人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow Peng , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
摘要翻译： 提供了一种用于验证半导体器件布局中存在可接受的器件特征梯度和器件特征差异的方法。 该方法提供了将设备布局划分成多个窗口并且测量或以其他方式确定每个窗口内的设备特征密度。 设备布局包括各种设备区域，并且该方法提供了将一个区域内的平均设备特征密度与周围区域或其他区域进行比较，并且还用于确定设备特征密度的梯度。 可以从特定设备区域到周围区域监视梯度。 用于执行该方法的指令可以存储在计算机可读存储介质上并由处理器执行。
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公开(公告)号：US20130346935A1
公开(公告)日：2013-12-26
申请号：US14012142
申请日：2013-08-28
申请人： Young-Chow PENG , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
发明人： Young-Chow PENG , Chung-Hui Chen , Chien-Hung Chen , Po-Zeng Kang
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , G03F1/36 , G03F1/70
摘要： A method for verifying that acceptable device feature gradients and device feature disparities are present in a semiconductor device layout, is provided. The method provides for dividing a device layout into a plurality of windows and measuring or otherwise determining the device feature density within each window. The device layout includes various device regions and the method provides for comparing an average device feature density within one region to surrounding areas or other regions and also for determining gradients of device feature densities. The gradients may be monitored from within a particular device region to surrounding regions. Instructions for carrying out the method may be stored on a computer readable storage medium and executed by a processor.
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公开(公告)号：US20120235208A1
公开(公告)日：2012-09-20
申请号：US13048411
申请日：2011-03-15
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译： 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。
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公开(公告)号：US09287252B2
公开(公告)日：2016-03-15
申请号：US13048411
申请日：2011-03-15
CPC分类号： H01L27/0207
摘要： A system and method for reducing density mismatch is disclosed. An embodiment comprises determining a conductor density and an active area density in a high density area and a low density area of a semiconductor device. Dummy material may be added to the low density area in order to raise the conductor density and the active area density, thereby reducing the internal density mismatches between the high density area and the low density area. Additionally, a similar process may be used to reduce external mismatches between different regions on the semiconductor substrate. Once these mismatches have been reduced, empty regions surrounding the different regions may additionally be filled in order to reduce the conductor density mismatch and the active area density mismatches.
摘要翻译： 公开了一种用于减小密度失配的系统和方法。 一个实施例包括确定半导体器件的高密度区域和低密度区域中的导体密度和有源面积密度。 为了提高导体密度和有效面积密度，可以向低密度区域添加虚拟材料，从而降低高密度区域和低密度区域之间的内部密度失配。 另外，可以使用类似的工艺来减少半导体衬底上不同区域之间的外部失配。 一旦这些失配被减小，则可以另外填充围绕不同区域的空区，以减少导体密度失配和有源区密度失配。
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